SPC563M64L7 datasheet(13/48 Pages) STMICROELECTRONICS

13 / 48 page

SPC563Mxx

Device overview

Doc ID 13850 Rev 6

13/48

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Configurable bus speed modes

–Bus monitor

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Configurable wait states

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System integration unit (SIU)

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Centralized GPIO control of 80 I/O pins

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Centralized pad control on a per-pin basis

Pin function selection

Configurable weak pull-up or pull-down

Drive strength

Slew rate

Hysteresis

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System reset monitoring and generation

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External interrupt inputs, filtering and control

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Critical Interrupt control

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Non-Maskable Interrupt control

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Internal multiplexer subblock (IMUX)

Allows flexible selection of eQADC trigger inputs (eTPU, eMIOS and external

signals)

Allows selection of interrupt requests between external pins and DSPI

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Error correction status module (ECSM)

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Configurable error-correcting codes (ECC) reporting

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Single-bit error correction reporting

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On-chip Flash memory

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Up to 1.5 MB flash memory, accessed via a 64-bit wide bus interface

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16 KB shadow block

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Fetch Accelerator

Provide single cycle flash access at 80 MHz

Quadruple 128-bit wide prefetch/burst buffers

Prefetch buffers can be configured to prefetch code or data or both

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Censorship protection scheme to prevent flash content visibility

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Flash divided into two independent arrays, allowing reading from one array while

erasing/programming the other array (used for EEPROM emulation)

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Memory block:

For SPC563M64: 18 blocks (4

× 16 KB, 2 × 32 KB, 2 × 64 KB, 10 × 128 KB)

For SPC563M60P: 14 blocks (4

× 16 KB, 2 × 32 KB, 2 × 64 KB, 6 × 128 KB)

For SPC563M54P: 12 blocks (4

× 16 KB, 2 × 32 KB, 2 × 64 KB, 4 × 128 KB)

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Hardware programming state machine

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On-chip static RAM

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For SPC563M64: 94 KB general purpose RAM of which 32 KB are on standby

power supply

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For SPC563M60P: 64 KB general purpose RAM of which 32 KB are on standby

power supply

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For SPC563M54P: 48 KB general purpose RAM of which 24 KB are on standby

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