SPC563M64L7 datasheet(39/48 Pages) STMICROELECTRONICS

39 / 48 page

SPC563Mxx

Device overview

Doc ID 13850 Rev 6

39/48

external address and data pins for internal visibility. The NPC block is an integration of

several individual Nexus blocks that are selected to provide the development support

interface for SPC563Mxx. The NPC block interfaces to the host processor (e200z335),

eTPU, and internal buses to provide development support as per the IEEE-ISTO 5001-2003

standard. The development support provided includes program trace and run-time access to

the MCUs internal memory map and access to the Power Architecture and eTPU internal

registers during halt. The Nexus interface also supports a JTAG only mode using only the

JTAG pins. SPC563Mxx in the production LQFP144 supports a 3.3 V reduced (4-bit wide)

Auxiliary port. These Nexus port pins can also be used as 5 V I/O signals to increase usable

I/O count of the device. When using this Nexus port as IO, Nexus trace is still possible using

calibration tool calibration. In the calibration tool calibration package, the full 12-bit Auxiliary

port is available.

Note:

In the calibration tool package, the full Nexus Auxiliary port shares balls with the addresses

of the calibration bus. Therefore multiplexed address/data bus mode must be used for the

calibration bus when using full width Nexus trace in calibration tool assembly.

SPC563M64L7 Datasheet(PDF) 39 Page - STMicroelectronics