STM32F101XF datasheet(17/117 Pages) STMICROELECTRONICS

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STM32F101xF, STM32F101xG

Description

2.3.10

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock is available when necessary (for example with

failure of an indirectly used external oscillator).

Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2)

domain and the low-speed APB (APB1) domain. The maximum frequency of the AHB and

APB domains is 36 MHz. See Figure 2 for details on the clock tree.

2.3.11

Boot modes

At startup, boot pins are used to select one of three boot options:

•

Boot from user Flash: you have an option to boot from any of two memory banks. By

default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash

memory bank 2 by setting a bit in the option bytes.

•

Boot from system memory

•

Boot from embedded SRAM

The bootloader is located in system memory. It is used to reprogram the Flash memory by

using USART1.

2.3.12

Power supply schemes

•

VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through VDD pins.

•

VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset

blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or

DAC is used). VDDA and VSSA must be connected to VDD and VSS, respectively.

•

VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when VDD is not present.

For more details on how to connect power pins, refer to Figure 9: Power supply scheme.

2.3.13

Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be

generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is

higher than the VPVD threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to

Table 12: Embedded reset and power control block characteristics for the values of

VPOR/PDR and VPVD.

STM32F101XF Datasheet(PDF) 17 Page - STMicroelectronics

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