DP8473 datasheet(13/28 Pages) NSC

13 / 28 page

Processor Software Interface (Continued)

both be set before a byte can be read from the Data Regis-

ter during the Result Phase

If there is information to be transferred during the Execution

Phase there are three methods that can be used The DMA

mode is used if the system has a DMA controller This al-

lows the mP to do other things during the Execution Phase

data transfer If DMA is not used an interrupt can be issued

for each byte transferred during the Execution Phase If in-

terrupts are not used the Main Status Register can be

polled to indicate when a byte transfer is required

DMA MODE

If the DMA mode is selected a DMA request will be gener-

ated in the Execution Phase when each byte is ready to be

transferred To enable DMA operations during the Execu-

tion Phase the DMA mode bit in the Specify Command

must be enabled and the DMA signals must be enabled in

the Drive Control Register The DMA controller should re-

spond to the DMA request with a DMA acknowledge and a

read or write strobe The DMA request will be cleared by the

active edge of the DMA acknowledge After the last byte is

transferred an interrupt is generated indicating the begin-

ning of the Result Phase During DMA operations the Chip

Select input must be held high TC is asserted to terminate

an operation Due to the internal gating TC is only recog-

nized when the DAK input is low

INTERRUPT MODE

If the non-DMA mode is selected an interrupt will be gener-

ated in the Execution Phase when each byte is ready to be

transferred The Main Status Register should be read to ver-

ify that the interrupt is for a data transfer Bits 5 and 7 of the

Main Status Register will be set The interrupt will be

cleared when the byte is transferred to or from the Data

allotted by Table VII If the byte is not transferred within the

time allotted an Overrun Error will be indicated in the Result

Phase when the command terminates at the end of the cur-

rent sector

An interrupt will also be generated after the last byte is

transferred This indicates the beginning of the Result

Phase Bits 7 and 6 of the Main Status Register will be set

and bit 5 will be clear This interrupt will be cleared by read-

ing the first byte in the Result Phase

SOFTWARE POLLING

If the non-DMA mode is selected and interrupts are not suit-

able the mP can poll the Main Status Register during the

Execution Phase to determine when a byte is ready to be

transferred In the non-DMA mode bit 7 of the Main Status

the data transfer is similar to the Interrupt Mode described

above

Command Description Table

READ DATA

Command Phase

MT MFM SK

IPS

HD DR1 DR0

Track Number

Drive Head Number

Sector Number

Number of Bytes per Sector

End of Track Sector Number

Intersector Gap Length

Data Length

Note 1

Result Phase

Status Register 0

Status Register 1

Status Register 2

Track Number

Head Number

Sector Number

BytesSector

READ ID

Command Phase

MFM

001010

HD DR1 DR0

Result Phase

Status Register 0

Status Register 1

Status Register 2

Track Number

Head Number

Sector Number

BytesSector

FORMAT A TRACK

Command Phase

MFM

001101

HD DR1 DR0

Number of Bytes per Sector

Number of Sectors per Track

Format Gap

Data Pattern

Result Phase

Status Register 0

Status Register 1

Status Register 2

Track Number

Head Number

Sector Number

BytesSector

DP8473 Datasheet(PDF) 13 Page - National Semiconductor (TI)

DP8473 Datasheet(HTML) 13 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL