AS4C64M8D2 datasheet(23/59 Pages) ALSC

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AS4C64M8D2

Confidential

Rev. 1.0

Feb. /2014

Table 24. IDD specification parameters and test conditions

(VDD = 1.8V  0.1V, TOPER = 0~95 C)

Parameter & Test Condition

Symbol

-25

-3

Unit

Max.

Operating one bank active-precharge current:

tCK =tCK (min), tRC = tRC (min), tRAS = tRAS(min); CKE is HIGH, CS# is

HIGH between valid commands; Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

IDD0

Operating one bank active-read-precharge current:

IOUT = 0mA; BL = 4, CL = CL (min), AL = 0; tCK = tCK (min),tRC = tRC (min),

tRAS = tRAS(min), tRCD = tRCD (min);CKE is HIGH, CS# is HIGH between

valid commands; Address bus inputs are switching; Data pattern is same

as IDD4W

IDD1

Precharge power-down current:

All banks idle;tCK =tCK (min); CKE is LOW; Other control and address bus

inputs are STABLE; Data bus inputs are FLOATING

IDD2P

Precharge quiet standby current:

All banks idle; tCK =tCK (min); CKE is HIGH, CS# is HIGH; Other control

and address bus inputs are STABLE; Data bus inputs are FLOATING

IDD2Q

Precharge standby current:

All banks idle; tCK = tCK (min); CKE is HIGH, CS# is HIGH; Other control

and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING

IDD2N

Active power-down current:

All banks open; tCK =tCK (min); CKE is LOW; Other control

and address bus inputs are STABLE; Data bus inputs are

FLOATING

MRS(A12)=0

IDD3P

MRS(A12)=1

Active standby current:

All banks open; tCK = tCK(min), tRAS = tRAS (max), tRP = tRP (min); CKE is

HIGH, CS# is HIGH between valid commands; Other control and address

bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD3N

Operating burst write current:

All banks open, continuous burst writes; BL = 4, CL = CL (min), AL = 0;

tCK= tCK (min), tRAS = tRAS (max), tRP = tRP (min); CKE is HIGH, CS# is

HIGH between valid commands; Address bus inputs are switching; Data

bus inputs are switching

IDD4W

120

110

Operating burst read current:

All banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL

(min), AL = 0; tCK = tCK (min), tRAS = tRAS (max), tRP = tRP (min); CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

IDD4R

130

120

Burst refresh current:

tCK = tCK (min); refresh command at every tRFC (min) interval; CKE is

HIGH, CS# is HIGH between valid commands; Other control and address

bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD5

Self refresh current:

CK and CK# at 0V; CKE ≤ 0.2V;Other control and address bus inputs are

FLOATING; Data bus inputs are FLOATING

IDD6

Operating bank interleave read current:

All bank interleaving reads, IOUT= 0mA; BL = 4, CL = CL (min), AL =tRCD

(min) - 1 x tCK (min); tCK = tCK (min), tRC = tRC (min), tRRD = tRRD (min), tRCD

= tRCD (min); CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are STABLE during DESELECTs. Data pattern is

same as IDD4R

IDD7

200

180

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