AS4C64M8D2 datasheet(9/59 Pages) ALSC

9 / 59 page

AS4C64M8D2

Confidential

Rev. 1.0

Feb. /2014

 Mode Register Set(MRS)

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS

latency, burst length, burst sequence, test mode, DLL reset, WR, and various vendor specific options to make

DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the

mode register must be programmed during initialization for proper operation. The mode register is written by

asserting LOW on CS#, RAS#, CAS#, WE#, BA0 and BA1, while controlling the state of address pins A0 - A13.

The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the mode

during normal operation as long as all bank are in the precharge state.The mode register is divided into various

fields depending on functionality.

- Burst Length Field (A2, A1, A0)

This field specifies the data length of column access and selects the Burst Length.

- Addressing Mode Select Field (A3)

The Addressing Mode can be Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave Mode

support burst length of 4 and 8.

- CAS Latency Field (A6, A5, A4)

This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The

minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying the

following formula must be programmed into this field. (tCAC(min) ≦ CAS Latency X tCK)

- Test Mode Field (A7); DLL Reset Mode Field (A8)

These two bits must be programmed to "00" in normal operation.

- Write recovery Field (A11, A10, A9)

The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation. The WR register is

used by the DDR2 SDRAM during WRITE with auto precharge operation.

- Active Power down Field (A12)

PD mode enables the user to determine the active power-down mode, which determines performance versus

power savings. does not apply to precharge PD mode.

- (BA0-BA1): Bank addresses to define MRS selection.

Table 5. Mode Register Bitmap

BA1 BA0 A13 A12 A11 A10 A9

A0 Address Field

DLL TM

CAS Latency

Burst Length

Mode Register

DLL Reset

Mode

Burst Type

A2 A1 A0 BL

Normal

Sequential

Yes

Test

Interleave

NOTE 1: For DDR2-667/800, WR min is determined by tCK (avg) max and WR max is determined by tCK(avg) min. WR [cycles]

= RU {tWR[ns]/tCK(avg)[ns]}, where RU stands for round up. The mode register must be programmed to this

value.This is also used with tRP to determine tDAL.

NOTE 2: A13 are reserved for future use and must be set to 0 when programming the MR.

A12 Active power down exit time

Write recovery for autoprecharge

Fast exit (use tXARD)

A11

A10

WR(cycles)

CAS Latency

Slow exit (use tXARDS)

Reserved

BA1

BA0

MRS Mode

Reserved

EMR(1)

EMR(2)

EMR(3)

Reserved

AS4C64M8D2 Datasheet(PDF) 9 Page - Alliance Semiconductor Corporation

AS4C64M8D2 Datasheet(HTML) 9 Page - Alliance Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL