AS7C316096C

Rev. 1.0

2048K X 8 BIT HIGH SPEED CMOS SRAM

Confidential

7

Rev 1.0 / May 2014

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)

Dout

Din

Data Valid

(4)

High-Z

WE#

CE#

Address

(4)

WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)

Dout

Din

Data Valid

(4)

High-Z

WE#

CE#

Address

Notes :

1.WE#,CE#, LB#, UB# must be high during all address transitions.

2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.

on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.