PC87415 datasheet(26/42 Pages) NSC

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70 Functional Description (Continued)

74212 Bus Master Reads

The device arbitrates onto the bus and waits for a grant

When the bus is granted the device reads the descriptor

from system memory and loads the address pointer and

byte count It then begins to read data from system memory

and buffering it in the posted write buffers until the buffer is

full When the buffer is full the device will release the PCI

bus When the device sees data in the buffer it begins to

write to the drive The device will request the PCI bus when-

ever the posted write buffer is either empty or half full If the

posted write buffer is empty (initial condition or due to an-

other master on the PCI bus) then the device reads in 4

Dwords from memory filling the buffers If the posted write

buffer is half full then the device reads in 2 Dwords from

memory filling the buffers When the byte count is 0 and it

was the last descriptor (EOT is 1) the device relinquishes

the bus (after the write FIFO is filled) while the write buffers

are being emptied out onto the IDE bus If it wasn’t the last

descriptor (EOT is 0) the device reads the new descriptor

from memory while the device is writing out to the drive the

contents of the write buffers

Figure 6 shows the DMA flow

The total PCI bus utilization for this type of transfer can be

calculated by the following equation

Bus Utilization e ARB a(Read Descriptor) a Tr a 3 Trb

255

ARB a Tr a Trb

Where

ARB e number of clocks for arbitration

Read Descriptor e number of clocks to read descriptors

from system memory

Tr e number of clocks for first non burst read

Trb e number of clocks for read burst

TLF12497 – 31

FIGURE 6 Bus Master ReadsScenario 1

7422 Scenario 2

The device requests the bus and no one else is on the bus

(the bus is idle) While the transfer takes place another

master requests the bus The latency timer is set to 2 ms

74221 Bus Master Writes

The device arbitrates for the PCI bus and at the same time

begins reading the data from the drive and filling the pre-

fetch buffers After the bus is granted the device reads the

descriptor from memory loads the address pointer and byte

count and then releases the bus When the prefetch buffer

is half full the device arbitrates onto the PCI bus and starts

writing out the prefetch data (2 Dwords) out onto the PCI

bus When the prefetch buffer is emptied onto the PCI bus

the device releases the PCI bus If another device becomes

a bus master while the device is writing out to memory the

device will continue prefetching data from the drive until the

prefetch buffers are full at which time it stops prefetching

The device continues to request the bus if the prefetch buff-

ers are full When it receives a grant the device writes out

the data (4 Dwords) from the prefetch buffers until the buffer

is empty When the prefetch buffer is empty and the byte

count is 0 and it was the last descriptor (EOT is 1) the

device relinquishes the bus If it wasn’t the last descriptor

(EOT is 0) the device continues prefetching from the drive

while reading the new descriptor from memory

Figure 7

shows the DMA flow

TLF12497 – 32

FIGURE 7 Bus Master WritesScenario 2

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