PC87415 datasheet(18/42 Pages) NSC

18 / 42 page

60 Bus Master IDE Control and Status Registers (Continued)

Offset from

Description

BAR4

RESERVED

CHANNEL 2 BUS MASTER IDE STATUS REGISTER

Writes to this register cause bit(s) to be reset Bits 1

and 2 are reset whenever the register is written with a ‘‘1’’ in the corresponding bit location Default value is

00h

Bit 0 Bus Master IDE Active This bit is set when the Start bit is written to the Bus Master IDE Command

region is set in the region descriptor It is also cleared when the Start bit is cleared in the Bus Master

IDE Command Register

Bit 1 Error This bit is set when the controller encounters an error in transferring data tofrom memory This

bit is cleared whena1is written to it by software

Bit 2 Interrupt This bit is set by the rising edge of CH2

INT This bit is cleared whena1is written to it by

software

Bit 3 – 4 Reserved

Bit 5 Drive 1 DMA Capable Bus Master IDE transfers to drive 1 on channel 2 are qualified by this bit

0 Drive 1 is not DMA capable

1 Drive 1 is DMA capable

Bit 6 Drive 2 DMA Capable Bus Master IDE transfers to drive 2 on channel 2 are qualified by this bit

0 Drive 2 is not DMA capable

1 Drive 2 is DMA capable

Bit 7 Simplex only This read-only bit is always 0 indicating that both channels can operate independently

and can be used at the same time

Reserved

0C-0F

CHANNEL 2 BUS MASTER IDE PRD TABLE ADDRESS

Default value is 00000000h

Bit 0 – 1 Reserved

Bit 2 – 31 Base address of channel 2 Descriptor table Corresponds to AD 312

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PC87415 Datasheet(PDF) 18 Page - National Semiconductor (TI)