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IDT5V928 Datasheet(PDF) 4 Page - Integrated Device Technology

Part # IDT5V928
Description  8 OUTPUT CLOCK GENERATOR
PDF  6 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT5V928 Datasheet(HTML) 4 Page - Integrated Device Technology

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INDUSTRIALTEMPERATURERANGE
IDT5V928
8OUTPUTCLOCKGENERATOR
INPUT TIMING REQUIREMENTS
Symbol
Description(1)
Min.
Max.
Unit
tR,tF
Maximum input rise and fall time, 0.8V to 2V(2)
10
ns/V
tPWC
Input clock pulse, HIGH or LOW(2)
2—
ns
DH
Inputdutycycle(2)
10
90
%
fOSC
XTALoscillatorfrequency
40
MHz
fIN
Inputfrequency(2)
50/N
160/N
MHz
NOTES:
1. Where pulse width implied by DH is less than the tPWC limit, tPWC limit applies,
2. When using a clock input.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
Min.
Typ.
Max
Unit
IDD_PD
Power Down Current
VDD = Max.
500
µA
S[1:0] = HH
OE = L; REF = L; X1 = L
Alloutputsunloaded
∆IDD
SupplyCurrentperInput
VDD = Max., VIN = 3V
30
µA
IDD
Dynamic Supply Current
VDD = 3.6V
130
mA
S[1:0] = LL
OE = L
FOUT = 150MHz
Alloutputsunloaded
NOTE:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
tR,tF
RiseTime,FallTime
0.8V to 2V
0.7
1.5
ns
dT
Output/Duty Cycle
VT = VDDQ/2
45
50
55
%
fOUT
≥≥≥≥≥ 100MHz, all N
-200
200
tPD
REF to Q0(1)
VT = VDDQ/2
50 < fOUT < 160MHz, N
≤ 4
-200
200
ps
50 < fOUT < 160MHz, N
≥≥≥≥≥ 4.25
-350
350
tSK
Output to Output Skew (Q0 to Q1:7)
Equalloads
200
ps
tJ
Cycle - Cycle Jitter
fOUT
≥≥≥≥≥ 100MHz
-100
100
ps
fOUT
OutputFrequency
50
160
MHz
NOTE:
1. When using a clock input.



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