AD9684 datasheet(63/65 Pages) AD

63 / 65 page

AD9684

Data Sheet

Reg.

Addr.

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Notes

0x568

LVDS

output

mode

Frame clock mode (only

used when in output data

mode is in byte mode)

00 = frame clock always

off

01 = frame clock always

10 = reserved

11 = frame clock

conditionally on based

on PN23 sequence

Output data mode

000 = parallel mode (one converter)

001 = parallel interleaved mode (two

converters)

010 = parallel channel multiplexed

(even/odd) mode (one converter)

011 = parallel channel multiplexed

(even/odd) mode (two converters)

100 = byte mode (one converter)

101 = byte mode (two converters)

110 = byte mode (four converters)

Others = reserved

0x00

0x569

Digital

clock

output

adjust

DCO phase adjustment

0x0: 0°

0x1: 90°

0x2: 180°

0x3: 270°

0x01

0x56A

Output

Parallel

Driver

Adjust 1

LVDS output drive current adjust

000 = 2 mA

001 = 2.25 mA

010 = 2.5 mA

011 = 2.75 mA

100 = 3.0 mA

101 = 3.25 mA

110 = 3.5 mA (default)

111 = 3.75 mA

0x4C

0x05B

Output

Parallel

Driver

Adjust 2

Output slew rate

control of LVDS driver

Interface

00 = 80 ps

01 = 150 ps

10 = 200 ps

11 = 250 ps

0x00

Rev. 0 | Page 62 of 64

AD9684 Datasheet(PDF) 63 Page - Analog Devices

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