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AD9684

Data Sheet

CLK+

DCO± (DATA CLOCK OUTPUT)

0° PHASE ADJUST

DCO± (DATA CLOCK OUTPUT)

180° PHASE ADJUST

SYNC+

APERTURE DELAY

N + x

N + 36

N + 37

N + 38

CHANNEL A D12±/D13±

CHANNEL A D0±/D1±

CHANNEL B D12±/D13±

CHANNEL B D0±/D1±

CONVERTERS

SAMPLE

[N]

VIN±x

STATUS

CLK–

SYNC–

STATUS+

(OVERRANGE/STATUS BIT)

STATUS–

tCLK

tDCO

tPD

tSKEWF

tSKEWR

CONVERTERS

SAMPLE

[N]

CONVERTERS

SAMPLE

[N + 1]

CONVERTERS

SAMPLE

[N + 1]

CONVERTERS

SAMPLE

[N + 2]

SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF

THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET

S[N – y]

(ODD BITS)

S[N]

(ODD BITS)

S[N – x]

(EVEN BITS)

S[N]

(EVEN BITS)

S[N + 1]

(ODD BITS)

S[N + 1]

(EVEN BITS)

S[N + 2]

(EVEN BITS)

S[N – 1]

(ODD BITS)

S[N – y]

(ODD BITS)

S[N]

(ODD BITS)

S[N – x]

(EVEN BITS)

S[N]

(EVEN BITS)

S[N + 1]

(ODD BITS)

S[N + 1]

(EVEN BITS)

S[N + 2]

(EVEN BITS)

S[N – 1]

(ODD BITS)

STATUS BIT SELECTED BY

IN THE REGISTER MAP

CONSTANT LATENCY = X CLK CYCLES

Figure 7. Channel Multiplexed (Even/Odd) Mode—Two Converters, ≤14-Bit Data, Output Sample Rate < 625 MSPS

Rev. 0 | Page 12 of 64

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