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LED171596ARSLR Datasheet(PDF) 32 Page - Texas Instruments |
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LED171596ARSLR Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 153 page ![]() 32 LED171596A SNVSAY2 – OCTOBER 2017 www.ti.com Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 7.6.1.1 CONFIG_PWM Register (Address = 0h) [reset = 1Fh] CONFIG_PWM is shown in Figure 26 and described in Table 8. Return to Summary Table. Figure 26. CONFIG_PWM Register 15 14 13 12 11 10 9 8 RESERVED pwm_input_edg e_sel pwm_input_hys teresis R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 pwm_input_hysteresis enable_pwm_d etector pwm_freq_sel pwm_phase_shift_config RESERVED R/W-0h R/W-0h R/W-1h R/W-3h R/W-3h Table 8. CONFIG_PWM Register Field Descriptions Bit Field Type Reset Description 15-10 RESERVED R/W 0h 9 pwm_input_edge_sel R/W 0h PWM period is measured: 0 - from rising edge to rising edge 1 - from falling edge to falling edge 8-6 pwm_input_hysteresis R/W 0h PWM hysteresis selection sets the minimum allowable change to the input. Hysteresis is monitoring direction of change and if direction is changing then hysteresis will apply. If a smaller change is detected to opposite direction, it is ignored. With hysteresis the constant changing between two brightness values is avoided if there is small jitter in the input signal. Hysteresis is selected with pwm_input_hysteresis bits in register CONFIG_PWM. Hysteresis is calculated from pwm detector 16-bit output value. Using a higher hysteresis setting is recommended with high PWM input frequencies.; Hysteresis (decimal), calculated from 16 bit value 000 - off 001 - 15 010 - 31 011 - 63 100 - 127 101 - 255 110 - 511 111 - 1023 5 enable_pwm_detector R/W 0h PWM input detector enable 4 pwm_freq_sel R/W 1h PWM Frequency selector: 0 - 20 kHz 1 - 10 kHz 3-2 pwm_phase_shift_config R/W 3h PWM phaseshifting 00 - off 01 - 1 clock cycles 10 - 2 clock cycles 11 - 3 clock cycles 1-0 RESERVED R/W 3h NOTE: When updating other fields in this register the 2 lsb reset value must be preserved! |
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