AD9993BBCZ datasheet(24/57 Pages) AD

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Data Sheet

AD9993

Rev. A | Page 23 of 56

Table 9 specifies the time between the ADC LVDS data lane

output transitions and the DDR DCO clock edge 50% transition

point.

Table 9. ADC DDR LVDS Data and Strobe Output Setup and

Hold Times Relative to DCO (Guaranteed)

Parameter

Minimum

Unit

|tSU|

400

|tHOLD|

430

Data Period

1000

LVDS LANE TESTING USING PRBS

One pseudorandom binary sequence (PRBS) generator is

included for each ADC LVDS lane and one PRBS detector on

each DAC LVDS lane. The designs for the generator and

detector are implemented as a 23rd-order pseudorandom noise

(PN23) sequence defined by the generator polynomial x23 + x18 + 1.

The initial seed of the generator is programmable so that each

lane can output different values if started simultaneously. The

four seed registers are indexed as described in the ADC Register

Update Indexing section.

DAC PRBS test results are read back on the DAC_A_PRBS_ERRx

and DAC_B_PRBS_ERRx error counter registers. The DAC

input PRBS error counters are enabled and the error counters

cleared by the bits in the DAC_PRBS_CTRL register. ADC

output lane PRBS generation is controlled by the bits in the

PRBS_GEN_CTRL register.

POWER MODE PROGRAMMING

The AD9993 has a POWER_MODES register that allows the

user to place sections of the chip into different power modes.

The PDWN_PIN_FUNC bit programs the function of the

PDWN pin. By default, assertion of PDWN causes the AD9993

to go into full power-down. The clock generator, indexed

ADCs, DACs, and PLL synthesizer are all powered down at

reset. The indexed ADCs have four power modes. See the ADC

INTERRUPT REQUEST OPERATION

The AD9993 provides an interrupt request signal, ALERT. It is

used to notify the user system of significant on-chip events. The

ALERT pin is an open-drain, active low output.

Eight different event flags provide visibility into the device.

These raw events are located in the INT_RAW register. These

raw events are always latched in the INT register. If the event is

left unmasked, the latched event triggers an external interrupt

on ALERT. INTEN is the interrupt enable register. When an

event is masked, the INT register captures the event in latched

form. A masked event does not cause ALERT to go true.

The eight events that trigger an interrupt (if enabled) are



PLL lock lost



PLL locked



FIFO Warning 1



FIFO Warning 2



ADC A overrange



ADC B overrange



ADC C overrange



ADC D overrange

Interrupt Service Routine

For the interrupt service routine, interrupt request management

starts by selecting the set of events that require host interven-

tion or monitoring using the bits in the INTEN register. For

events requiring host intervention, upon ALERT activation, run

the following routine to clear an interrupt request:

Read the status of the latched bits in the INT register that

are being monitored.

Monitor the unlatched status bits in the INT_RAW register

directly if needed.

Perform any actions that may be required to clear the

interrupt(s).

Read the INT_RAW bits to verify that the actions taken

have cleared the event.

Clear the interrupt by writing 1 to the event flag bit in the

INT register.

TEMPERATURE SENSOR

The AD9993 has a diode-based temperature sensor for

measuring the temperature of the die. The temperature reading

is accessed using the TS_RD_LSB and TS_RD_MSB registers.

The temperature of the die can be calculated as

106

237





Temp[15:0]

Die

DIE

where:

TDIE is the die temperature in degrees Celsius.

Die Temp is the concatenated 16-bit contents of the TD_RD_LSB

and TD_RD_MSB registers. The temperature accuracy is ±7°C

typical over the −40°C to +85°C range with one point

temperature calibration against a known temperature. A typical

plot of the die temperature code readback vs. die temperature is

shown in Figure 31.

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