MAX9201ESE datasheet(3/8 Pages) MAXIM

3 / 8 page

Low Cost, 7ns, Low-Power

Voltage Comparators

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Note 1: All devices are 100% production tested at TA = +25°C. All temperature limits are guaranteed by design.

Note 2: Inferred by CMRR test.

Note 3: Tested for +4.75V < VCC < +5.25V, and -5.25V < VEE < -4.75V with VDD = +5V, although permissible analog power-supply

range is 4.75V < VCC < +10.5V for single supply operation with VEE grounded.

Note 4: Specification does not apply to MAX9201.

Note 5: ICC tested for 4.75V < VCC < +10.5V with VEE grounded. IEE tested for -5.25V < VEE < -4.75V with VCC = +5V. IDD tested for

+4.75V < VDD < +5.25V with all comparator outputs low, worst-case condition.

Note 6: Guaranteed by design. Times are for 100mV step inputs (see propagation delay characteristics in Figures 2 and 3)

Note 7: Maximum difference in propagation delay between two comparators in the MAX9201/MAX9202.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

MAX9201

3.4

5.0

MAX9202

1.8

3.0

Negative Analog Supply

Current

IEE

Note 5

MAX9203

1.0

1.6

MAX9201

3.0

MAX9202

1.5

Digital Supply Current

IDD

Note 5

MAX9203

0.5

0.8

MAX9201

MAX9202

Power Dissipation

VCC = VDD = +5V,

VEE = 0V

MAX9203

TIMING CHARACTERISTICS

(VCC = +5V, VEE = -5V, VDD = +5V, GND = 0, VCM = 0, LATCH_ = logic high, TA = -40°C to +85°C. Typical values are at

TA = +25°C, unless otherwise noted.) (Notes 1, 6)

ELECTRICAL CHARACTERISTICS (continued)

(VCC = +5V, VEE = -5V, VDD = +5V, GND = 0, VCM = 0, LATCH_ = logic high, TA = -40°C to +85°C. Typical values are at TA = +25°C,

unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TA = +25

°C7

Input-to-Output High

Response Time

tPD+

VOD = 5mV,

CL = 15pF,

IOUT = 2mA

TA = -40

°C to +85°C12

TA = +25

°C7

Input-to-Output Low

Response Time

tPD-

VOD = 5mV,

CL = 15pF,

IOUT = 2mA

TA = -40

°C to +85°C12

Rise Time

CL = 15pF,

IOUT = 2mA

TA = +25

°C

2.0

Fall Time

CL = 15pF,

IOUT = 2mA

TA = +25

°C

1.0

TA = +25

°C

0.5

1.5

Difference in Response Time

Between Outputs

∆tPD

Note 7

TA = -40

°C to +85°C

2.5

Latch Disable to Output High

Delay

tPD+(D)

Note 4

Latch Disable to Output Low

Delay

tPD-(D)

Note 4

Minimum Setup Time

Note 4

Minimum Hold Time

Note 4

Minimum Latch Disable

Pulse Width

tPW(D)

Note 4

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