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7

Low Cost, 7ns, Low-Power

Voltage Comparators

Power Supplies

The MAX9201/MAX9202/MAX9203 can be powered

from separate analog and digital supplies or from a sin-

gle +5V supply. The analog supply can range from +5V

(Figures 1a and 1b) or from a split ±5V supply (Figure

In high-speed, mixed-signal applications where a com-

mon ground is shared, a noisy digital environment can

adversely affect the analog input signal. When set up with

separate supplies, the MAX9201/MAX9202/MAX9203

isolate analog and digital signals by providing a separate

Definition of Terms

Input Offset Voltage: Voltage applied be-

tween the two input terminals to obtain TTL

logic threshold (+1.4V) at the output.

Input Voltage Pulse Amplitude: Usually set

to 100mV for comparator specifications.

Input Voltage Overdrive: Usually set to 5mV

specifications.

Input to Output High Delay: The propagation

delay measured from the time the input signal

crosses the input offset voltage to the TTL

logic threshold (+1.4V) of an output low to high

transition.

Input to Output Low Delay: The propagation

delay measured from the time the input signal

crosses the input offset voltage to the TTL

logic threshold (+1.4V) of an output high to low

transition.

propagation delay measured from the latch

signal crossing the TTL logic threshold

(+1.4V) in a low to high transition to the point

of the output crossing TTL threshold (+1.4V)

in a low to high transition.

tpd- (D) Latch Disable to Output Low Delay: The

propagation delay measured from the latch

signal crossing the TTL threshold (+1.4V) in a

low to high transition to the point of the output

crossing TTL threshold (+1.4V) in a high to

low transition.

Minimum Setup Time: The minimum time,

before the negative transition of the latch sig-

nal, that an input signal change must be pre-

sent in order to be acquired and held at the

outputs.

Minimum Hold Time: The minimum time,

after the negative transition of the latch sig-

nal, that an input signal must remain

unchanged in order to be acquired and held

at the output.

Minimum Latch Disable Pulse Width: The

minimum time that the latch signal must

remain high in order to acquire and hold an

input signal change.

Figure 2. MAX9201/MAX9202/MAX9203 Diagram

LATCH

ENABLE

INPUT

LATCH

COMPARE

LATCH

LATCH

COMPARE

COMPARATOR

OUTPUT

1.4V

1.4V

5ns/div

OUTPUT

INPUT

50mV/div

1V/div

0V

0V