AT89C5130A-RDTIM datasheet(95/184 Pages) ATMEL

95 / 184 page

AT89C5130A/31A-M

4337C–USB–02/05

Figure 42. Data Transmission Format (CPHA = 0)

Figure 43. Data Transmission Format (CPHA = 1)

Figure 44. CPHA/SS Timing

As shown in Figure 43, the first SCK edge is the MSB capture strobe. Therefore the

Slave must begin driving its data before the first SCK edge, and a falling edge on the SS

pin is used to start the transmission. The SS pin must be toggled high and then low

between each byte transmitted (Figure 40).

Figure 44 shows an SPI transmission in which CPHA is’1’. In this case, the Master

begins driving its MOSI pin on the first SCK edge. Therefore the Slave uses the first

SCK edge as a start transmission signal. The SS pin can remain low between transmis-

sions (Figure 39). This format may be preferable in systems having only one Master and

only one Slave driving the MISO data line.

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

bit6

bit5

bit4

bit3

bit2

bit1

MSB

LSB

Capture point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (internal)

SCK cycle number

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

bit6

bit5

bit4

bit3

bit2

bit1

MSB

LSB

567

Capture point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (internal)

SCK cycle number

Byte 1

Byte 2

Byte 3

MISO/MOSI

Master SS

Slave SS

(CPHA = 1)

Slave SS

(CPHA = 0)

AT89C5130A-RDTIM Datasheet(PDF) 95 Page - ATMEL Corporation

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