AT89C5130A-RDTIM datasheet(14/184 Pages) ATMEL

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AT89C5130A/31A-M

4337C–USB–02/05

Figure 6. Crystal Connection

PLL

PLL Description

The AT89C5130A/31A-M PLL is used to generate internal high frequency clock (the

USB Clock) synchronized with an external low-frequency (the Peripheral Clock). The

PLL clock is used to generate the USB interface clock. Figure 7 shows the internal

structure of the PLL.

The PFLD block is the Phase Frequency Comparator and Lock Detector. This block

makes the comparison between the reference clock coming from the N divider and the

reverse clock coming from the R divider and generates some pulses on the Up or Down

signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON

in PLLCON register (see Figure 7) is set.

The CHP block is the Charge Pump that generates the voltage reference for the VCO by

injecting or extracting charges from the external filter connected on PLLF pin (see

Fi gure 8 ) . Value of the filter components ar e detailed in the Section “ DC

Characteristics”.

The VCO block is the Voltage Controlled Oscillator controlled by the voltage V

REF pro-

duced by the charge pump. It generates a square wave signal: the PLL clock.

Figure 7. PLL Block Diagram and Symbol

Figure 8. PLL Filter Connection

The typical values are: R = 100

Ω, C1 = 10 nf, C2 = 2.2 nF.

VSS

PLLEN

PLLCON.1

N3:0

N divider

R divider

VCO

USB Clock

USBclk

OSCclk

()

-----------------------------------------------

OSC

CLOCK

PFLD

PLOCK

PLLCON.0

PLLF

CHP

Vref

Down

R3:0

USB

CLOCK

USB Clock Symbol

VSS

PLLF

VSS

AT89C5130A-RDTIM Datasheet(PDF) 14 Page - ATMEL Corporation

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