VITESSE

SEMICONDUCTOR CORPORATION

®

Advance Product Information

VSC7182

Quad Transceiver

for Gigabit Ethernet and Fibre Channel

Page 14

G52307-0, Rev 2.2

10/10/00

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

N14

PLUP

INPUT - TTL: Parallel Loopback Enable Input. RXi is input to the CRU for Channel x

(normal operation) when PLUP is LOW. When HIGH, internal loopback paths from

TXi to RXi are enabled. Refer to Table 2.

C9

SLPN

INPUT - TTL: Serial Loopback Enable Input. Normal operation when HIGH. When

LOW, SI+/- is looped back to TXi+/- internally for diagnostic purposes. Refer to Table

2 and related description.

R3

P4

K4

D5

LPNA

LPNB

LPNC

LPND

INPUT - TTL: Loopback Enable Pins. When LPNi is LOW, PLUP/SLPN impact

Channel x. When HIGH, PLUP/SLPN have no effect on Channel x.

R17

SYNC

INPUT - TTL: Enables SYNi and Word Alignment when HIGH. When LOW, keeps

current word alignment and disables SYNi (always LOW).

F2

A4

B10

B15

SYNCA

SYNCB

SYNCC

SYNCD

OUTPUT - TTL: Comma Detect for Channel x. This output goes HIGH for half of an

RCi1 period to indicate that RXi[0:9] contains a “comma” character

(‘0011111XXX’). SYNi will go HIGH only during a cycle when RCi0 is rising. SYNi

is enabled when SYNC is HIGH.

P9

R9

CAP0

CAP1

ANALOG: Loop Filter capacitor for the Clock Multiply Unit. Typically 0.1

µF

connected between CAP0 and CAP1. Amplitude is less than 3.3V.

T17

TCK

INPUT - TTL: JTAG Test Clock

D9

TMS

INPUT - TTL: JTAG Test Mode Select

R15

TRSTN

INPUT - TTL: JTAG Test Reset, Active LOW

P15

TDI

INPUT - TTL: JTAG Test Data Input

K2

TDO

OUTPUT - TTL: JTAG Test Data Output

T9

VDDA

Analog Power Supply

R8

VSSA

Analog Ground. Tie to common ground plane with VSS.

A2,A10,C14

G4,J14,K16

L4,N15,R4

R14,T3

T4,T14,U5

VDD

Digital Logic Power Supply

C4, D3,F3

A9, B7, C5

A13, A16, C11

C15, E14, G17

VDDT

TTL Output Power Supply

T5

T7

T11

T13

VDDPA

VDDPB

VDDPC

VDDPD

PECL I/O Power Supply for Channel x.

Pin

Name

Description