LP6304B datasheet(11/12 Pages) POWER

11 / 12 page

LP6304B-01

May.-2013

Email: marketing@lowpowersemi.com

www.lowpowersemi.com

Page 11 of 12

Preliminary Datasheet

LP6304B

PCB Layout

Layout is very critical for PMIC designs. For LP6304B PCB layout considerations, please refer to the following

suggestions to get best performance.



It is suggested to use 4-layer PCB layout and place LX plane and output plane on the top layer, place VIN

plane in the inner layer.



The top layer SMD input and output capacitors ground plane should be connected to the internal ground layer

and bottom ground plane individually by using vias.



The GND should be connected to inner ground layer directly by using via.



High current path traces need to be widened.



Place the input capacitors as close as possible to the VINx pin to reduce noise interference.



Keep the feedback path (from VOUTX to FBx) away from the noise node (ex. LXx). LXx is a high current noise

node. Complete the layout by using short and wide traces.



The top layer exposed pad ground plane should be connected to the internal ground layer and bottom ground

plane by using a number of vias to improve thermal performance.



Place the input capacitors as close as possible to the VINx pin to reduce noise interference.

LP6304B Datasheet(PDF) 11 Page - Lowpower Semiconductor inc