1

2

A

3

4

5

6

B

C

D

E

F

G

H

J

K

L

25

26

27

28

29

30

31

3

DLP4710

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DLPS125 – NOVEMBER 2018

Product Folder Links: DLP4710

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Copyright © 2018, Texas Instruments Incorporated

(1)

Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard

No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.

(2)

Net trace lengths inside the package:

Relative dielectric constant for the FQL ceramic package is 9.8.

Propagation speed = 11.8 / sqrt (9.8) = 3.769 inches/ns.

Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.

5 Pin Configuration and Functions

FQL Package

100-Pin LGA

Bottom View

PIN

TYPE

SIGNAL

DATA RATE

DESCRIPTION

PACKAGE NET

NAME

NO.

DATA INPUTS

D_AN(0)

G3

I

SubLVDS

Double

Data, Negative

5.01

D_AN(1)

F4

I

SubLVDS

Double

Data, Negative

2.03

D_AN(2)

E3

I

SubLVDS

Double

Data, Negative

2.41

D_AN(3)

E6

I

SubLVDS

Double

Data, Negative

4.71

D_AN(4)

J5

I

SubLVDS

Double

Data, Negative

3.23

D_AN(5)

L5

I

SubLVDS

Double

Data, Negative

3.87

D_AN(6)

G5

I

SubLVDS

Double

Data, Negative

6.32

D_AN(7)

L3

I

SubLVDS

Double

Data, Negative

1.84

D_AP(0)

H3

I

SubLVDS

Double

Data, Positive

5.01

D_AP(1)

G4

I

SubLVDS

Double

Data, Positive

2.03

D_AP(2)

E4

I

SubLVDS

Double

Data, Positive

2.41

D_AP(3)

E5

I

SubLVDS

Double

Data, Positive

4.71