DLP4710AFQL datasheet(13/43 Pages) TI1

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DLP4710

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DLPS125 – NOVEMBER 2018

Product Folder Links: DLP4710

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Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS(2)

MIN

TYP

MAX

UNIT

(10) LPSDR specification is for pin LS_RDATA.

IIL

Low–level input current

VDD = 1.95 V; VI = 0 V

–100

IIH

High–level input current

VDD = 1.95 V; VI = 1.95 V

100

LPSDR OUTPUT(10)

VOH

DC output high voltage

IOH = –2 mA

0.8 × VDD

VOL

DC output low voltage

IOL = 2 mA

0.2 × VDD

CAPACITANCE

CIN

Input capacitance LPSDR

ƒ = 1 MHz

Input capacitance SubLVDS

ƒ = 1 MHz

COUT

Output capacitance

ƒ = 1 MHz

CRESET

Reset group capacitance

ƒ = 1 MHz; (1080 × 240)

micromirrors

400

450

(1)

Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 3.

(2)

Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 3.

(3)

Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.

6.7 Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

MIN

NOM

MAX

UNIT

LPSDR

Rise slew rate(1)

(30% to 80%) × VDD, Figure 3

V/ns

tƒ

Fall slew rate(1)

(70% to 20%) × VDD, Figure 3

V/ns

Rise slew rate(2)

(20% to 80%) × VDD, Figure 3

0.25

V/ns

tƒ

Fall slew rate(2)

(80% to 20%) × VDD, Figure 3

0.25

V/ns

Cycle time LS_CLK,

Figure 2

7.7

8.3

tW(H)

Pulse duration LS_CLK high

50% to 50% reference points,

Figure 2

3.1

tW(L)

Pulse duration LS_CLK low

50% to 50% reference points,

Figure 2

3.1

tsu

Setup time

LS_WDATA valid before LS_CLK

↑,

Figure 2

1.5

t h

Hold time

LS_WDATA valid after LS_CLK

↑,

Figure 2

1.5

tWINDOW

Window time(1) (3)

Setup time + Hold time, Figure 2

3.0

tDERATING

Window time derating(1) (3)

For each 0.25 V/ns reduction in slew

rate below 1 V/ns, Figure 5

0.35

SubLVDS

Rise slew rate

20% to 80% reference points,

Figure 4

0.7

V/ns

tƒ

Fall slew rate

80% to 20% reference points,

Figure 4

0.7

V/ns

Cycle time DCLK,

Figure 6

1.79

1.85

tW(H)

Pulse duration DCLK high

50% to 50% reference points,

Figure 6

0.79

tW(L)

Pulse duration DCLK low

50% to 50% reference points,

Figure 6

0.79

tsu

Setup time

D(0:7) valid before

DCLK

↑ or DCLK ↓, Figure 6

t h

Hold time

D(0:7) valid after

DCLK

↑ or DCLK ↓, Figure 6

DLP4710AFQL Datasheet(PDF) 13 Page - Texas Instruments

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