ADC0803, ADC0805

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH DIFFERENTIAL INPUTS

SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986

4

POST OFFICE BOX 655303

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VOH

High level output voltage

All outputs

VCC = 4.75 V,

IOH = – 360 µA

2.4

V

VOH

High-level output voltage

DB and INTR

VCC = 4.75 V,

IOH = – 10 µA

4.5

V

Data outputs

VCC = 4.75 V,

IOL = 1.6 mA

0.4

VOL

Low-level output voltage

INTR output

VCC = 4.75 V,

IOL = 1 mA

0.4

V

CLK OUT

VCC = 4.75 V,

IOL = 360 µA

0.4

VT+

Clock positive-going threshold voltage

2.7

3.1

3.5

V

VT–

Clock negative-going threshold voltage

1.5

1.8

2.1

V

VT+ –VT– Clock input hysteresis

0.6

1.3

2

V

IIH

High-level input current

0.005

1

µA

IIL

Low-level input current

– 0.005

–1

µA

IOZ

Off state output current

VO = 0

–3

µA

IOZ

Off-state output current

VO = 5 V

3

µA

IOHS

Short-current output current

Output high

VO = 0,

TA = 25°C

– 4.5

–6

mA

IOLS

Short-circuit output current

Output low

VO = 5 V,

TA = 25°C

9

16

mA

ICC

Supply current plus reference current

VREF/2 = open,

TA = 25°C,

CS = 5 V

1.1

1.8

mA

RREF/2

Input resistance to reference ladder

See Note 6

2.5

8

k

Ω

Ci

Input capacitance (control)

5

7.5

pF

Co

Output capacitance (DB)

5

7.5

pF

NOTE 6:

Resistance is calculated from the current drawn from a 5-V supply applied to ANLG GND and REF/2.

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

Supply-voltage-variation error

VCC = 4.5 to 5.5 V,

See Note 7

+1/16

±1/8

LSB

Total adusted error

ADC0803

With full scale adjust

See Notes 7 and 8

±1/4

LSB

Total adusted error

ADC0803

With full-scale adjust,

See Notes 7 and 8

±1/2

LSB

Total unadjusted error

ADC0805

VREF/2 = 2.5 V,

See Notes 7 and 8

±1/2

LSB

Total unadjusted error

ADC0805

VREF/2 open,

See Notes 7 and 8

±1

LSB

DC common-mode error

See Notes 7 and 8

±1/16

±1/8

LSB

ten

Output enable time

TA = 25°C,

CL = 100 pF

135

200

ns

tdis

Output disable time

TA = 25°C, CL = 10 pF,

RL = 10 kΩ

125

200

ns

td(INTR) Delay time to reset INTR

TA = 25°C

300

450

nx

t

Conversion cycle time

fclock = 100 kHz to 1.46 MHz,

73

clock

tconv

Conversion cycle time

TA = 25°C,

See Note 9

73

cycles

CR

Free-running conversion rate

INTR connected to WR,

CS at 0 V

66

8770

conv/s

† All typical values are at TA = 25°C.

NOTES:

7. These parameters are specified over the recommended analog input voltage range.

8. All errors are measured with reference to an ideal straight line through the end-points of the analog-to-digital transfer characteristics.

9. Although internal conversion is completed in 64 clock periods, a CS or WR low-to-high transition is followed by 1 to 8 clock periods

before conversion starts. After conversion is complete, part of another clock period is required before a high-to-low transition of INTR

completes the cycle.