MT7697DN datasheet(12/84 Pages) ETC2

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MT7697D

Internet-of-Things Wireless Connectivity

Page 12 of 84

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Functional Description

2.1

Overview

2.2

Power Management Unit

A single regulated 3.3V power supply is required for the MT7697D. It could be from DC-DC converter

to convert higher voltage supply to 3.3V or boost from a lower voltage supply to 3.3V.

The Power Management Unit (PMU) contains Under-Voltage Lockout (UVLO) circuit, several Low

Drop-out Regulators (LDOs), a highly efficient buck converter, and a reference band-gap circuit. The

circuits are optimized for low quiescent current, low drop-out voltage, efficient line/load regulation,

high ripple rejection, and low output noise.

BUCK/SLDOH

(3.3V)

CLDO/SLDOL

(1.6V)

AVDD45_BUCK

AVDD45_MISC

AVDD12_VCORE

DVDD11

AVDD16_CLDO

LXBK

DVDDIO

AVDD16_WF0_AFE

AVDD16_XO

AVDD16_BT

RF LDO/RF

core (1.6V)

IO (3.3V)

AVDD33_WF0_A_TX

AVDD33_WF0_A_PA

AVDD33_WF0_G_TX

AVDD33_WF0_G_PA

AVDD33_BT

RF(3.3V)

1.6V

1.15V

3.3V

Digital core

(1.15V)

AVSS45_BUCK

VSS

AVDD25_ALDO_OUT

ALDO

(3.3V)

ADC

(2.5V)

AVDD25_AUXADC

ELDO

(3.3V to 2.5V)

AVSS25_AUXADC

VSS

2.5V

PMU_DIO33_OUT

3.3V

Figure 2-1. Chip Power Block Diagram

2.2.1

PMU Architecture

The PMU integrates 5 LDOs and one buck converter.

The four LDOs are CLDO, ALDO, high-voltage SLDO (SLDO-H) and low-voltage SLDO (SLDO-L). SLDO

stands for sleep mode LDO, and CLDO stands for digital core LDO. The buck converter converts

1.6~1.8V output to other subsystems in MT7697D. It can be operated in PFM mode or PWM mode.

Through an external on-board LC filter (2.2uH inductor and 10uF cap), it outputs a low ripple

1.6~1.8V to Wi-Fi RF system, Bluetooth RF system, and CLDO. CLDO is under BUCK domain, and then

it outputs 1.15V for whole chip digital logics used. ALDO is also from 3.3V chip supply input and

generates 2.5V for the auxiliary ADC. The two SLDOs have 1.8V and 0.85V output voltage respectively.

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