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MT7697DN Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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MT7697DN Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
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7 / 84 page ![]() MT7697D Internet-of-Things Wireless Connectivity © 2016 MediaTek Inc. Page 7 of 84 This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s). Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited. Table 3-8. Bluetooth LE Transmitter Specifications...............................................................................67 Table 4-1 Absolute Maximum Rating .................................................................................................... 68 Table 4-2. Recommended Operating Range .........................................................................................68 Table 4-3. DC Characteristics................................................................................................................. 68 Table 4-4. XTAL Oscillator Requirements ..............................................................................................69 Table 4-5. PMU Electrical Characteristics..............................................................................................69 Table 4-6. Auxiliary ADC Specifications ................................................................................................70 Table 4-7. Thermal Characteristics........................................................................................................ 72 Table 5-1. Pin Map ................................................................................................................................ 73 Table 5-2. Pin Descriptions.................................................................................................................... 74 Table 5-3. Pin Multiplexing.................................................................................................................... 77 Table 5-4. Boostrap Option– Flash Access Mode..................................................................................82 Table 5-5. Bootstrap Option – XTAL Clock Mode ..................................................................................82 Table 5-6. Bootstrap Option – 32KHz Clock Mode................................................................................82 Table 5-7. Bookstrap Option — Chip Mode ..........................................................................................82 Table 5-8. Ordering Information ........................................................................................................... 83 List of Figures Figure 1-1. System-on-Chip Block Diagram...........................................................................................11 Figure 2-1. Chip Power Block Diagram.................................................................................................. 12 Figure 2-2. MT7697D Power State ........................................................................................................ 15 Figure 2-3. Clock Generation Block Diagram.........................................................................................17 Figure 2-4. Clock Domains in N9 and CM4 Peripherals.........................................................................19 Figure 2-5. Reset Structure ................................................................................................................... 20 Figure 2-6. CM4 Subsystem – Bus Fabric ..............................................................................................22 Figure 2-7. Virtual FIFO Concept ........................................................................................................... 24 Figure 2-8. PMU Power-on Sequence ................................................................................................... 30 Figure 2-9. WDT Structure .................................................................................................................... 31 Figure 2-10. Sleep/Wakeup Sequence ................................................................................................. 32 Figure 2-11. AGPIO/GPIO Block Diagram (Left: AGPIO; Right: GPIO)....................................................39 |
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