AD9929BBCZ datasheet(43/64 Pages) AD

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AD9929

Rev. A | Page 43 of 64

V1 TO V4 AND SUBCK OUTPUT POLARITIES

As shown in Figure 41, the XV1 to XV4 and XSUBCK are

output signals from the AD9929 timing generator, whereas the

V1 to V1 and SUBCK are output signals from the AD9929

vertical driver. The V1 to V4 and SUBCK polarities are not the

same as the internal XV1 to XV4 and XSUBCK polarities

configured by the AD9929 registers. Table 28 through Table 32

describe the output polarities for these signals versus their input

levels. These tables must be referred to when determining the

example of the V3 output.

Table 28. V1 Output Polarity

V-Driver Input

V1 Output

XV1

XVSG1

VH1

VM1

Table 29. V2 Output Polarity

V-Driver Input

V2 Output

XV2

VM2

Table 30. SUBCK Output Polarity

V-Driver Input

SUBCK Output

XSUBCK

VH2

TIMING

GENERATOR

XV1

XV2

XV3

XV4

XVSG1

XSUBCK

SUBCK

XVSG2

V-DRIVER

LOGIC

V-DRIVER

BUFFERS

V-DRIVER

Figure 41. Internal XV1 to XV4 and XSUBCK Signals

Table 31. V3 Output Polarity

V-Driver Input

V3 Output

XV3

XVSG2

VH1

VM1

Table 32. V4 Output Polarity

V-Driver Input

V4 Output

XV4

VM2

XVSG1

XVSG3

VH1

VM1

tPMH

tR2

tPHM

tF1

50%

10%

90%

10%

90%

50%

XV1

XV3

tPLM1

tR1

10%

90%

tPML1

tF2

10%

90%

Figure 42. V1 and V3 Transmission Delays and Rise Times

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