LS1020A datasheet(22/71 Pages) FREESCALE

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Architecture

TWR-LS1021A Reference Manual, Rev. 0

Freescale Semiconductor

2-7

pin-sampled configuration driver logic to insure hardware-spec compliance; Refer Section

“(Re)Configuration” for further details.

2.5

Device configuration

The processor uses hardware-sampled pins to configure various portions of the device. The remainder are

configured from data in the Reset Configuration Word (RCW).

TWR-LS1021A configuration pins are described in Table 2-3.

2.6

Clocks

The clocks section specify various clocks:

•

SYSCLK(single-ended and differential)

•

DDRCLK (single-ended)

•

SERDES clocks (2 independent options)

•

Ethernet clocks

•

USB clock

The architecture of the clock section is shown in in Figure 2-6.

Table 2-3. Configuration options

Configuration

Signal

Nets Sampled

Switch

Preset

CPLD Register

Description

cfg_rcw_src[0:8]

IFC_AD[8:15],

IFC_CLE

SW2[1:4]

0x05:

cfg_rcw_src1[0:7]

0x06:

cfg_rcw_src2[0]

Specifies RCW fetch location by

SW2[1:4] decode.

cfg_dram_type

IFC_A[21]

n/a

Specifies DDR3L or DDR4.

Affects GVDD power supply.

cfg_ifc_te

IFC_TE

n/a

IFC TE signal enable; not normally

used.

cfg_gpinput[0:7]

IFC_AD[0:7]

n/a

Application defined.

cfg_eng_use0

IFC_WE0_B

n/a

Differential or single ended clock

selection.

cfg_eng_use1

IFC_OE_B

n/a

Reserved

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