LS1020A datasheet(61/71 Pages) FREESCALE

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CPLD System Controller Architecture

TWR-LS1021A Reference Manual, Rev. 0

4-4

Freescale Semiconductor

0x05

R/W

cfg_rcw_src1

0x06

R/W

cfg_rcw_src2

0x07

R/W

vbank

0x08

R/W

gpio

0x09

R/W

i2c3_ifc_mux

0x0A

R/W

mux_spi2

0x0B

R/W

can3_usb2_mux

0x0C

R/W

qe_lcd_mux

0x0D

R/W

serdes_mux

0x0E

R/W

global_rst

0x0F

R/W

elec_cs

0x10

lvdd_vsel

0x11

R/W

soft_mux_on2

0x12

R/W

nor_qspi_mux

Table 4-3. CPLD BCSR register detail map

Base Address

Offset

Access

Type

Description

Default Value

0x00

Bit [3:0]: CPLD Major Revision Register

Bit [7:4]: Reserved

cpld_ver

0x02

0x01

Bit [3:0]: CPLD Minor Revision Register

Bit [7:4]: Reserved

cpld_ver_sub

0x00

0x02

Bit [3:0]: PCBA Revision Register

Bit [7:4]: Reserved

pcba_ver

0x03

R/W

Writing this register to reset system with

reserving CPLD

registers value and overriding physical

switches on the board

Bit [0]: 0 system running(Default)

1 system reset

Bit [7:1]: Reserved

system_rst

0x00

Table 4-2. CPLD BCSR register block map

Base Address

Offset

Access

Type

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