LS1020A datasheet(25/71 Pages) FREESCALE

Part #	LS1020A

Description	TWR-LS1021A Reference Manual

PDF	71 Pages

Scroll/Zoom	100%

Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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25 / 71 page

Architecture

TWR-LS1021A Reference Manual, Rev. 0

2-10

Freescale Semiconductor

Figure 2-7. DDR3L memory architecture

2.8

SerDes port

The LS1021A / LS1020A SerDes block provides four high-speed serial communication lanes supporting

a variety of protocols, including:

•

SGMII1.25 / 3.125 Gbps

•

PCI Express (PEX) Gen 11X / 2X / 4X2.5 Gbps

•

PCI Express (PEX) Gen 21X / 2X / 4X5 Gbps

•

SATA1X1.5 / 3 Gbps

An overview of the SerDes protocols supported on LS1021A is shown in Table 2-6.

SerDes lanes are routed through high-speed multiplexers, the CBTL02043A. The multiplexers route

SerDes lanes and connect them to SATA connectors or PCI Express slots for evaluation of PCI Express.

Table 2-6. LS1021A SerDes protocols

2 bits Protocol

SerDes

0x10

PCIe1 SATA

PCIe2

0x20

PCIe1 VeTSec1 PCIe2

VeTsec2

0x30

PCIe1 SATA

VeTSec1 VeTsec2

0x70

PCIe1 SATA

PCIe2

VeTsec2

LS1020A Datasheet(PDF) 25 Page - Freescale Semiconductor, Inc