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STM8S Datasheet(PDF) 227 Page - STMicroelectronics |
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STM8S Datasheet(HTML) 227 Page - STMicroelectronics |
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227 / 467 page  DocID14587 Rev 14 227/467 RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5) 261 Output stage Refer to Section 17.5.4: Output stage on page 171, Section 17.5.5: Forced output mode on page 172, Section 17.5.7: PWM mode on page 174. Note: As the clock/trigger controller and the associated TIMx_CR2 and TIMx_SMCR registers are not implemented in TIM2/TIM3, the one-pulse mode (described in Section 17.5.7: PWM mode) is not available in TIM2/TIM3. As shown in Figure 87. TIMx outputs have no deadtime or complementary outputs. Figure 87. Output stage The output stage generates an intermediate waveform which is then used for reference: OCxREF (active high). Polarity acts at the end of the chain (see Figure 88). Figure 88. Output stage of channel 1 |
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