STM8S datasheet(229/467 Pages) STMICROELECTRONICS

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RM0016

16-bit general purpose timers (TIM2, TIM3, TIM5)

261

18.6

TIM2/TIM3/TIM5 registers

18.6.1

Control register 1 (TIMx_CR1)

Address offset: 0x00

Reset value: 0x00

654

3210

ARPE

Reserved

OPM

URS

UDIS

CEN

Bit 7 ARPE: Auto-reload preload enable

0: TIMx_ARR register is not buffered through a preload register. It can be written directly

1: TIMx_ARR register is buffered through a preload register

Bits 6:4 Reserved

Bit 3 OPM: One-pulse mode (1)

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the CEN bit)

Bit 2 URS: Update request source

0: When enabled by the UDIS bit, the UIF bit is set and an update interrupt request is sent when one

of the following events occurs:

–

Registers are updated (counter overflow/underflow)

–

UG bit is set by software

–

Update event is generated through the clock/trigger controller

1: When enabled by the UDIS bit, the UIF bit is set and an update interrupt request is sent only when

registers are updated (counter overflow/underflow).

Bit 1 UDIS: Update disable

0: A UEV is generated as soon as a counter overflow occurs or a software update is generated or an

hardware reset is generated by the clock/trigger mode controller. Buffered registers are then loaded

with their preload values.

1: A UEV is not generated, shadow registers keep their value (ARR, PSC, CCRi). The counter and

the prescaler are re-initialized if the UG bit is set.

Bit 0 CEN: Counter enable

0: Counter disabled

1: Counter enabled

1. One-pulse mode is not available on TIM2/TIM3 but the OPM bit can be used for other purposes (for example, to stop the

counter properly).

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