STM8S datasheet(233/467 Pages) STMICROELECTRONICS

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RM0016

16-bit general purpose timers (TIM2, TIM3, TIM5)

261

18.6.5

Status register 1 (TIMx_SR1)

Address offset: 0x02 or 0x04 (TIM2), 0x02 (TIM3), 0x04 (TIM5); for TIM2 address see

Section

Reset value: 0x00

654

3210

Reserved

TIF

Reserved

CC3IF

CC2IF

CC1IF

UIF

rc_w0

Bit 7 Reserved

Bit 6 TIF: Trigger interrupt flag

This flag is set by hardware on a trigger event (active edge is detected on TRGI signal and both

edges are detected when gated mode is selected). It is cleared by software.

0: No trigger event has occurred

1: Trigger interrupt pending

Note: In TIM2/TIM3 this bit is reserved.

Bits 5:4 Reserved, must be kept cleared

BIt 3 CC3IF: Capture/compare 3 interrupt flag

Refer to CC1IF description.

Bit 2 CC2IF: Capture/compare 2 interrupt flag

Refer to CC1IF description.

Bit 1 CC1IF: Capture/compare 1 interrupt flag

If channel CC1 is configured as output:

This flag is set by hardware when the counter matches the compare value. It is cleared by software.

0: No match

1: The content of the counter TIMx_CNT has matched the content of the TIMx_CCR1 register

If channel CC1 is configured as input:

This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1L

0: No input capture has occurred

1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1

which matches the selected polarity).

Bit 0 UIF: Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update has occurred

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow if UDIS = 0 in the TIMx_CR1 register

– When CNT is re-initialized by software using the UG bit in TIMx_EGR register, if URS = 0 and

UDIS = 0 in the TIMx_CR1 register.

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