STM8S datasheet(231/467 Pages) STMICROELECTRONICS

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RM0016

16-bit general purpose timers (TIM2, TIM3, TIM5)

261

18.6.3

Slave mode control register (TIM5_SMCR)

Address offset: 0x02

Reset value: 0x00

Note:

This register is only available in TIM5, see Table 42 on page 250.

654

3210

MSM

TS[2:0]

Reserved

SMS[2:0]

Bit 7 MSM Master/slave mode

0: No action

1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization

between timers (through TRGO).

Bits 6:4 TS[2:0] Trigger selection

This bit field selects the trigger input to be used to synchronize the counter.

000: Internal trigger ITR0 connected to TIM6 TRGO (*)

001: Internal trigger ITR1 connected to TIM6 TRGO (*)

010: Reserved

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

(*) 8K low-density devices unless otherwise specified.

Note: These bits must only be changed when they are not used (e.g. when SMS = 000) to avoid

wrong edge detections at the transition.

Bit 3 Reserved.

Bits 2:0 SMS[2:0] Clock/trigger/slave mode selection

When external signals are selected, the active edge of the trigger signal (TRGI) is linked to the

polarity selected on the external input (see Input Control register and Control Register description).

000: Clock/trigger controller disabled - if CEN = 1 then the prescaler is clocked directly by the

internal clock.

001, 010 and 011: Reserved

100: Trigger reset mode - Rising edge of the selected trigger signal (TRGI) reinitializes the counter

and generates an update of the registers.

101: Gated mode - The counter clock is enabled when the trigger signal (TRGI) is high. The counter

stops (but is not reset) as soon as the trigger becomes low. Both the start and stop of the counter are

controlled.

110: Trigger mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only

the start of the counter is controlled.

111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter

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