STM8S datasheet(258/467 Pages) STMICROELECTRONICS

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8-bit basic timer (TIM4, TIM6)

RM0016

258/467

DocID14587 Rev 14

19.6.4

Interrupt enable register (TIMx_IER)

Address offset: 0x01 or 0x03 (TIM4), 0x03 (TIM6); for TIM4 address see Section 19.6.10

Reset value: 0x00

19.6.5

Status register 1 (TIMx_SR)

Address offset: 0x02 or 0x04 (TIM4), 0x04 (TIM6); for TIM4 address see Section 19.6.10

Reset value: 0x00

654

3210

Reserved

TIE

Reserved

UIE

rrw

Bit 7 Reserved, must be kept cleared

Bit 6 TIE: Trigger interrupt enable

0: Trigger Interrupt disabled

1: Trigger Interrupt enabled

Note: In TIM4 this bit is reserved.

Bits 5:1 Reserved, must be kept cleared

Bit 0 UIE: Update interrupt enable

0: Update interrupt disabled

1: Update interrupt enabled

654

3210

Reserved

TIF

Reserved

UIF

rc_w0

Bit 7 Reserved, must be kept cleared

Bit 6 TIF: Trigger interrupt flag.

This flag is set by hardware on a trigger event (the active edge is detected on the TRGI signal,

both edges are detected if gated mode is selected). It is cleared by software.

0: No trigger event has occurred

1: Trigger interrupt pending.

Note: In TIM4 this bit is reserved.

Bits 5:1 Reserved, must be kept cleared

Bit 0 UIF: Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update has occurred

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow if UDIS = 0 in the TIM4_CR1 register

– When CNT is re-initialized by software using the UG bit in the TIM4_EGR register, if URS = 0

and UDIS = 0 in the TIM4_CR1 register.

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