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STM8S Datasheet(PDF) 260 Page - STMicroelectronics

Part # STM8S
Description  STM8S Series and STM8AF Series 8-bit microcontrollers
PDF  467 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM8S Datasheet(HTML) 260 Page - STMicroelectronics

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8-bit basic timer (TIM4, TIM6)
RM0016
260/467
DocID14587 Rev 14
19.6.9
Auto-reload register (TIMx_ARR)
Address offset: 0x06 or 0x08 (TIM4), 0x08 (TIM6); for TIM4 address see Section 19.6.10
Reset value: 0xFF
19.6.10
TIM4/TIM6 register map and reset values
In some STM8S and STM8AF devices, TIM4 register locations at offset 0x01 and 0x02 are
reserved. In this case the TIM4_IER and subsequent registers in the TIM4 block are offset
by 2 more bytes. Refer to the datasheet for the product-specific register map.
Bits 7:3 Reserved, must be kept cleared
Bits 2:0 PSC[2:0]: Prescaler value
The prescaler value divides the CK_PSC clock frequency. The counter clock frequency fCK_CNT is
equal to fCK_PSC / 2(PSC[2:0]).
PSC contains the value which is loaded into the active prescaler register at each UEV (including
when the counter is cleared through the UG bit of TIM4_EGR).
Consequently, a UEV must be generated so that a new prescaler value can be taken into account.
7
654
3210
ARR[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 7:0 ARR[7:0]: Auto-reload value
Table 43. TIM4 register map
Address
offset
(product
dependent)
Register
name
765
43210
0x00 0x00
TIM4_CR1
Reset value
ARPE
0
-
0
-
0
-
0
OPM
0
URS
0
UDIS
0
CEN
0
-
0x01
Reserved
-
0x02
Reserved
0x01 0x03
TIM4_IER
Reset value
-
0
-
0
-
0
-
0
-
0
-
0
-
0
UIE
0
0x02 0x04
TIM4_SR
Reset value
-
0
-
0
-
0
-
0
-
0
-
0
-
0
UIF
0
0x03 0x05
TIM4_EGR
Reset value
-
0
-
0
-
0
-
0
-
0
-
0
-
0
UG
0
0x04 0x06
TIM4_CNTR
Reset value
CNT7
0
CNT6
0
CNT5
0
CNT4
0
CNT3
0
CNT
2
0
CNT1
0
CNT0
0
0x05 0x07
TIM4_PSCR
Reset value
-
0
-
0
-
0
-
0
-
0
PSC
2
0
PSC1
0
PSC0
0
0x06 0x08
TIM4_ARR
Reset value
ARR7
1
ARR6
1
ARR5
1
ARR4
1
ARR3
1
ARR2
1
ARR1
1
ARR0
1



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