STM8S datasheet(413/467 Pages) STMICROELECTRONICS

413 / 467 page

DocID14587 Rev 14

413/467

RM0016

Controller area network (beCAN)

427

23.11.15 Mailbox registers

This chapter describes the registers of the transmit and receive mailboxes. Refer to

Section 23.6.4: Message storage for detailed register mapping.

Transmit and receive mailboxes have the same registers except:

–

CAN_MCSR register in a transmit mailbox is replaced by CAN_MFMIR register in

a receive mailbox.

–

A receive mailbox is always write protected.

–

A transmit mailbox is write enabled only while empty (the corresponding TME bit in

the CAN_TPR register is set).

Caution:

As the mailbox registers usually have no defined reset value, the user should not rely on the

initial setup and should always fill all the configuration bits accordingly.

CAN message control/status register (CAN_MCSR)

Address offset: See Table 66. and Table 67.

Reset value: 0x00

Note:

This register is implemented only in transmit mailboxes. In receive mailboxes, the

CAN_MFMIR register is mapped at this location.

654

3210

Reserved

TERR

ALST

TXOK

RQCP

ABRQ

TXRQ

rc_w1

Bits 7:6 Reserved.

Bit 5 TERR Transmission error

This bit is updated by hardware after each transmission attempt.

0: The previous transmission was successful

1: The previous transmission failed due to an error

Bit 4 ALST Arbitration lost

This bit is updated by hardware after each transmission attempt.

0: The previous transmission was successful

1: The previous transmission failed due to an arbitration lost

Bit 3 TXOK Transmission OK

The hardware updates this bit after each transmission attempt.

0: The previous transmission failed

1: The previous transmission was successful

Note: This bit has the same value as the corresponding TXOKx bit in the CAN_TSR register.

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