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STM8S Datasheet(PDF) 414 Page - STMicroelectronics |
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STM8S Datasheet(HTML) 414 Page - STMicroelectronics |
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414 / 467 page  Controller area network (beCAN) RM0016 414/467 DocID14587 Rev 14 CAN mailbox filter match index register (CAN_MFMIR) Address offset: See Table 66. and Table 67. Reset value: 0xXX Note: This register is implemented only in receive mailboxes. In transmit mailboxes, the CAN_MCSR register is mapped at this location. Bit 2 RQCP Request completed Set by hardware when the last request (transmit or abort) has been performed. Cleared by software writing a “1” or by hardware on transmission request. Note: This bit has the same value as the corresponding RQCPx bit of the CAN_TSR register. Clearing this bit clears all the status bits (TXOK, ALST and TERR) in the CAN_MCSR register and the corresponding RQCPx and TXOKx bits in the CAN_TSR register. Bit 1 ABRQ Abort request for mailbox Set by software to abort the transmission request for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. Setting this bit has no effect when the mailbox is not pending for transmission. Bit 0 TXRQ Transmit mailbox request Set by software to request the transmission for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. 7 654 3210 FMI[7:0] r rrr rrrr Bits 7:0 FMI[7:0] Filter match index This register contains the index of the filter the message stored in the mailbox passed through. For more details on identifier filtering please refer to Section 23.6.3: Identifier filtering - Filter Match Index paragraph. |
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