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USB3450 Datasheet(PDF) 37 Page - SMSC Corporation

Part # USB3450
Description  HI-SPEED USB HOST OR DEVICE PHY WITH UTMIINTERFACE
PDF  40 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

USB3450 Datasheet(HTML) 37 Page - SMSC Corporation

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Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
SMSC USB3450
37
Revision 0.1 (05-11-05)
DATASHEET
7.12
Detection of Resume
Resume signaling always takes place in FS mode (TERMSELECT and XCVRSELECT = FS enabled),
so the behavior for a HS device is identical to that of a FS device. The Link uses the LINESTATE
signals to determine when the USB transitions from the 'J' to the 'K' state and finally to the terminating
FS EOP (SE0 for 1.25us-1.5µs.).
The resume signaling (FS 'K') will be asserted for at least 20ms. At the beginning of this period the
Link may negate SUSPENDN, allowing the transceiver (and its oscillator) to power up and stabilize.
The FS EOP condition is relatively short. Links that simply look for an SE0 condition to exit suspend
mode do not necessarily give the transceiver’s clock generator enough time to stabilize. It is
recommended that all Link implementations key off the 'J' to 'K' transition for exiting suspend mode
(SUSPENDN = 1). And within 1.25µs after the transition to the SE0 state (low-speed EOP) the Link
must enable normal operation, i.e. enter HS or FS mode depending on the mode the device was in
when it was suspended.
Figure 7.7 Resume Timing Behavior (HS Mode)
Table 7.9 Resume Timing Values (HS Mode)
TIMING
PARAMETER
DESCRIPTION
VALUE
T0
Internal device event initiating the resume
process
0 (reference)
T1
Device asserts FS 'K' on the bus to signal
resume request to downstream port
T0 < T1 < T0 + 10ms.
T2
The device releases FS 'K' on the bus. However
by this time the 'K' state is held by downstream
port.
T1 + 1.0ms < T2 < T1 + 15ms
T3
Downstream port asserts SE0.
T1 + 20ms
T4
Latest time at which a device, which was
previously in HS mode, must restore HS mode
after bus activity stops.
T3 + 1.33µs {2 Low-speed bit times}



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