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CY25568
Spread Spectrum Clock Generator
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07111 Rev. *A
06/21/01
Page 3 of 12
Approved Product
PIN CONFIGURATION
Figure 2. 16 Pin SOIC Pin Assignment
PIN DESCRIPTION
Pin
Function
Description
1
Xin/CLK
Clock, crystal or ceramic resonator input pin.
2VSS
Power Supply Ground.
3VSS
Power Supply Ground.
4S1
Digital Spread % control pin. 3-Level input (H-M-L). Default=M.
5S0
Digital Spread % control pin. 3-Level input (H-M-L). Default=M.
6SSCLK1
Output Clock. Refer to Table-6 for frequency programmability.
7REFOUT
Reference Clock Output. The same frequency as Xin/CLK input.
8SSCLK3
Output Clock. Refer to Table-6 for frequency programmability.
9SSCLK2
Output Clock. Refer to Table-6 for frequency programmability.
10
PD#
Power Down Control. Internally Pulled to VDD, Default=High.
11
FRSEL
Input Frequency Range Selection digital control input. 3-Level input (H-M-L). Default=M.
12
VDD
Positive Power Supply.
13
VDD
Positive Power Supply.
14
D0
3-Level (H-M-L) Digital output clock scaling control. Refer to Table-6. Default=M.
15
D1
3-Level (H-M-L) Digital output clock scaling control. Refer to Table-6. Default=M.
16
XOUT
Crystal or ceramic resonator output pin.
Table 2. Pin Description
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XOUT
D1
D0
VDD
VDD
FRSEL
PD#
SSCLK2
XIN/CLKIN
VSS
VSS
S1
S0
SSCLK1
REFOUT
SSCK3
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