TLE7258SJ datasheet(21/31 Pages) INFINEON

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TLE7258

Electrical Characteristics

Data Sheet

Rev. 1.1, 2015-08-20

Bus dominant output voltage

maximum load

BUS,do

–

1.4

2.0

TxD = 0 V; RL = 500 Ω;

S =7 V;

S =18 V;

4.8.9

Dynamic Transceiver Characteristics

Propagation delay:

LIN bus dominant to RxD “low”

LIN bus recessive to RxD “high”

rx_pdft

rx_pdr

3.5

μs

LIN Spec 2.2A (Par. 31)

RxD = 2.4 kΩ; CRxD = 20 pF

4.9.1

Receiver delay symmetry

rx_sym

-2

–

μs

LIN Spec 2.2A (Par. 32)

rx_sym = trx_pdf - trx_pdr;

RxD = 2.4 kΩ; CRxD = 20 pF

4.9.2

Dominant time for bus wake-up

WK,bus

–

150

μs

–

4.9.3

Delay time for mode change

MODE

––50

μs

4.9.4

TxD time-out

TxD

1828ms

–

4.9.5

TxD recessive time to release

transmitter

to,rec

––10

μs

4.9.6

Duty cycle D1

(for worst case at 20 kBit/s)

0.396 –

–

Duty cycle 1 5)

Rec(max) = 0.744 × VS;

Dom(max) =0.581 × VS;

S = 7.0 … 18 V; tbit = 50 μs;

D1 = t

bus_rec(min) / 2 × tbit;

LIN Spec 2.2A (Par. 27)

4.9.7

Duty cycle D1

for

S supply 5.5 V to 7.0 V

(for worst case at 20 kBit/s)

0.396 –

–

Duty cycle 1 5)

Rec(max) = 0.760 × VS;

Dom(max) = 0.593 × VS;

5.5 V <

S <7.0 V;

bit = 50 μs;

D1 = t

bus_rec(min) / 2 × tbit

4.9.8

Duty cycle D2

(for worst case at 20 kBit/s)

–

0.581

Duty cycle 2 5)

Rec(min)= 0.422 × VS;

Dom(min)= 0.284 × VS;

S = 7.6 … 18 V; tbit = 50 μs;

D2 = t

bus_rec(max) / 2 × tbit;

LIN Spec 2.2A (Par. 28)

4.9.9

Duty cycle D2

for

S supply 6.1 V to 7.6 V

(for worst case at 20 kBit/s)

–

0.581

Duty cycle 2 5)

Rec(min)= 0.410 × VS;

Dom(min)= 0.275 × VS;

6.1 V <

S <7.6 V;

bit = 50 μs;

D2 = t

bus_rec(max) / 2 × tbit

4.9.10

Table 6

Electrical Characteristics (cont’d)

5.5 V <

S <18V; RL = 500 Ω; -40°C < Tj <150°C;

all voltages with respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Symbol

Values

Unit Note / Test Condition

Num

ber

Min.

Typ.

Max.

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