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STM32WL55JC Datasheet(PDF) 73 Page - STMicroelectronics

Part # STM32WL55JC
Description  Multiprotocol LPWAN dual core 32-bit Arm® Cortex®-M4/M0 LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
PDF  145 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WL55JC Datasheet(HTML) 73 Page - STMicroelectronics

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DS13293 Rev 1
73/145
STM32WL55/54xx
Electrical characteristics
135
TXRMP
PA ramping time
Programmable
10
-
3400
µs
TS_TX
TX wakeup time
Frequency synthesizer
enabled
-
36 + PA ramping
-
1. For low-power PA, +15 dBm maximum RF output power can be reached with optimal settings.
Table 31. Sub-GHz radio transmit mode specifications (continued)
Symbol
Description
Conditions
Min
Typ
Max
Unit
Table 32. Sub-GHz radio power management specifications
Symbol
Description
Conditions
Frequency
(MHz)
Unit
470
490
868
TRPOR
Required POR reset pulse duration
For VDD ≥ 1.8 V
50
100
-
µs
VEOLL
End-of-life low-threshold voltage
-
1.81 1.89 1.96
V
VEOLH
End-of-life high-threshold voltage
-
1.86 1.94
2.1
VEOLD
End-of-life hysteresis voltage
VEOLH - VEOLL
50
53
56
mV
VREG
Main regulated supply
LDO or SMPS over process,
voltage and temperature range
1.47 1.55 1.62
V
LDTRSMPS
Load transient for ILSMPS 100 µA to
100 mA in 10 µs
LDO running
High BW mode
-
25
-
mV
Low BW mode
-
47
-
ILSMPS
SMPS load current
-
-
-
100
mA
IDDSMPS
SMPS quiescent current
SMPS high power, VDD = 3.3 V
-
538
-
µA
SMPS low power, VDD = 3.3 V
-
460
-
EFFSMPS
SMPS converter average efficiency
EFF = VREG x ILOAD /
VDDSMPS x IDD
SMPS 100 mA max VDD = 3.3 V,
ILSMPS = 6 mA
-71-
%
SMPS 100 mA max VDD = 3.3 V,
ILSMPS = 50 mA
-89-
SMPS 100 mA max VDD = 1.8 V,
ILSMPS = 6 mA
-88-
SMPS 100 mA max VDD = 2.0 V,
ILSMPS = 50 mA
-91-
SMPS 100 mA max VDD = 3.3 V,
ILSMPS = 100 mA
-86-
Cout
Shared between LDO and SMPS
±20 % tolerance
-
470
-
nF
Lout
SMPS inductor
-
-
15
-
µH
TSSMPS
Sleep and Sleep, SMPS startup time
For ILIM = 50 mA
-
70
-
µs



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