ADIS16446

Data Sheet

Rev. 0 | Page 4 of 23

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

2.0

V

0.8

V

±0.2

±10

µA

All Pins Except RST

40

60

µA

RST Pin

1

mA

10

pF

2.4

V

0.4

V

FLASH MEMORY

10,000

Cycles

20

Years

Time until new data is available

Power-On Start-Up Time

205

ms

90

ms

Flash Memory Back-Up Time

75

ms

Flash Memory Test Time

20

ms

Automatic Self-Test Time

SMPL_PRD = 0x0001

45

ms

CONVERSION RATE

xGYRO_OUT and xACCL_OUT

SMPL_PRD = 0x0001

819.2

SPS

Clock Accuracy

±3

%

0.8

1.1

kHz

POWER SUPPLY VOLTAGE RANGE

VDD

3.15

3.3

3.45

V

Power Supply Current

76

104

mA

1

The repeatability specifications represent analytical projections, which are based off of the following drift contributions and conditions: temperature hysteresis (−40°C

to +85°C), electronics drift (high temperature operating life test: 85°C, 500 hours), drift from temperature cycling (JESD22, Method A104-C, Method N, 500 cycles,

−40°C to +85°C), rate random walk (10 year projection), and broadband noise.

2

Bias repeatability describes a long-term behavior, over a variety of conditions. Short-term repeatability is related to the in-run bias stability and noise density

specifications.

3

X-ray exposure may degrade this performance metric.

4

The digital I/O signals are driven by an internal 3.3 V supply, and the inputs are 5 V tolerant.

5

Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, +85°C, and +125°C.

6

7

These times do not include thermal settling and internal filter response times (330 Hz bandwidth), which may affect overall accuracy.

8

The RST line must be held low for at least 10 µs to assure a proper reset and recovery sequence.

9

The sync input clock functions below the specified minimum value but at reduced performance levels.