AI01130C

18

A0-A17

W

DQ0-DQ14

VPP

VCC

M28F410

M28F420

G

E

VSS

15

RP

BYTE

DQ15A-1

Figure 1. Logic Diagram

March 1995

M28F410

M28F420

4 Megabit (x8 or x16, Block Erase) FLASH MEMORY

PRELIMINARY DATA

DUAL x8 and x16 ORGANIZATION

SMALL SIZE PLASTIC PACKAGES TSOP56

and SO44

MEMORY ERASE in BLOCKS

– One 16K Byte or 8K Word Boot Block (top or

bottom location) with hardware write and

erase protection

– Two 8K Byte or 4K Word Key Parameter

Blocks

– One 96K Byte or 48K Word Main Block

– Three 128K Byte or 64K Word Main Blocks

5V

± 10% SUPPLY VOLTAGE

12V

± 5% PROGRAMMING VOLTAGE

100,000 PROGRAM/ERASE CYCLES

PROGRAM/ERASE CONTROLLER

AUTOMATIC STATIC MODE

LOW POWER CONSUMPTION

–60

μA Typical in Standby

– 0.2

μA Typical in Deep Power Down

– 20/25mA Typical Operating Consumption

(Byte/Word)

HIGH SPEED ACCESS TIME: 70ns

EXTENDED TEMPERATURE RANGES

A0-A17

Address Inputs

DQ0-DQ7

Data Input / Outputs

DQ8-

DQ14

Data Input / Outputs

DQ15A-1

Data Input/Output or Address Input

E

Chip Enable

G

Output Enable

W

Write Enable

BYTE

Byte/Word Organization

RP

Reset/Power Down/Boot Block Unlock

Program & Erase Supply Voltage

Supply Voltage

Table 1. Signal Names

This is preliminary infor mationon a new product now in developmen t or undergoing evaluation. Details are subject to change without notice.

44

1

SO44 (M)

TSOP56 (N)

14 x 20mm

1/38