Power-Down

Jumper JU4 controls the power-management feature of

data converter U1. See Table 1 for jumper JU4 shunt

positions.

Clock

By default, the user-provided AC-coupled clock signal

applied to the EV kit CLOCK SMA connector is buffered

on board with two inverters (U4). In this mode, diode

D1 limits the amplitude of the clock signal. Overdriving

the clock input can increase the slew rate of the differ-

ential signal, thereby reducing clock jitter. The frequen-

cy of the signal should not exceed the maximum

sampling rate of the ADC. The sinusoidal input signal

ADC. The clock signal applied to the ADC can be

observed at test point TP10.

Optional Clock-Shaping Circuit

The EV kit also features an optional on-board clock-

shaping circuit that generates a clock signal with vari-

able duty cycle from the AC-coupled sine-wave signal

applied to the CLOCK SMA connector. The MAX9111

differential line receiver (U2) processes the clock input

signal and generates the required CMOS clock signal.

To use this circuitry, cut the trace on the printed circuit

(PC) board at R78 and install 0

Ω resistors at R35 and

R77. The signal’s duty cycle can be adjusted with poten-

tiometer R54. With a 3.3V clock supply voltage (CVDD),

a clock signal with a 50% duty cycle (recommended)

can be achieved by adjusting R54 until a voltage of

1.32V is produced across test points TP12 and TP16.

PLL Frequency Mode Selection

When driving the EV kit with clock signals lower than

the maximum specified sampling rate of the ADC, the

phased-locked-loop (PLL) circuit of the ADC must be

set accordingly. Refer to the PLL Inputs (PLL0–PLL3)

section in the ADC data sheet for further details about

the operation of the internal PLL. Jumpers JU5, JU6,

and JU13 control the PLL mode of the ADC. See Tables

2, 3, 4, or 5 for shunt positions. Configure jumpers JU5,

JU6, and JU13 accordingly and ensure that the clock

signal frequency falls between the minimum and maxi-

mum limits listed in Table 2 through Table 5.

MAX1434/MAX1436/MAX1437/MAX1438

Evaluation Kits

_______________________________________________________________________________________________________

5

SHUNT

POSITION

POWER-DOWN

CONNECTIONS

EV KIT FUNCTION

1-2

AVDD

ADC disabled

2-3*

GND

ADC enabled

Table 1. Power-Down Jumper Settings (JU4)

*

Default configuration: JU4 (2-3).

JUMPER

CLOCK INPUT RANGE

(MHz)

JU13

(PLL1)

JU6

(PLL2)

JU5

(PLL3)

MIN

MAX

2-3

2-3

2-3

Unused

2-3*

2-3*

1-2*

39.0

50.0

2-3

1-2

2-3

27.0

39.0

2-3

1-2

1-2

19.5

27.0

1-2

2-3

2-3

13.5

19.5

1-2

2-3

1-2

9.8

13.5

1-2

1-2

2-3

6.8

9.8

1-2

1-2

1-2

4.8

6.8

Table 2. MAX1434 PLL Jumper Settings

(JU5, JU6, JU13)

*

Default configuration: JU5, JU6 (2-3), JU13 (1-2).

JUMPER

CLOCK INPUT RANGE

(MHz)

JU13

(PLL1)

JU6

(PLL2)

JU5

(PLL3)

MIN

MAX

2-3

2-3

2-3

Unused

2-3*

2-3*

1-2*

32.5

40.0

2-3

1-2

2-3

22.5

32.5

2-3

1-2

1-2

16.3

22.5

1-2

2-3

2-3

11.3

16.3

1-2

2-3

1-2

8.1

11.3

1-2

1-2

2-3

5.6

8.1

1-2

1-2

1-2

4.0

5.6

*

Default configuration: JU5, JU6 (2-3), JU13 (1-2).

Table 3. MAX1436 PLL Jumper Settings

(JU5, JU6, JU13)