IMX6SDLCEC datasheet(46/169 Pages) NXP

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i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Electrical Characteristics

4.7.2

DDR I/O AC Parameters

Table 31 shows the AC parameters for DDR I/O operating in LPDDR2 mode. For details on supported

DDR memory configurations, see Section 4.9.4, “Multi-Mode DDR Controller (MMDC).

Table 30. General Purpose I/O AC Parameters 3.3 V Mode

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output Pad Transition Times, rise/fall

(Max Drive, DSE=101)

tr, tf

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

——

1.70/1.79

1.06/1.15

Output Pad Transition Times, rise/fall

(High Drive, DSE=011)

tr, tf

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

——

2.35/2.43

1.74/1.77

Output Pad Transition Times, rise/fall

(Medium Drive, DSE=010)

tr, tf

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

——

3.13/3.29

2.46/2.60

Output Pad Transition Times, rise/fall

(Low Drive. DSE=001)

tr, tf

15 pF Cload, slow slew rate

15 pF Cload, fast slew rate

——

5.14/5.57

4.77/5.15

Input Transition Times1

1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

trm

—

Table 31. DDR I/O LPDDR2 Mode AC Parameters1

1 Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.

Parameter

Symbol

Test Condition

Min

Max

Unit

AC input logic high

Vih(ac)

—

Vref + 0.22

OVDD

AC input logic low

Vil(ac)

—

Vref - 0.22

AC differential input high voltage2

2 Vid(ac) specifies the input differential voltage | Vtr - Vcp | required for switching, where Vtr is the “true” input signal and Vcp

is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).

Vidh(ac)

—

0.44

—

AC differential input low voltage

Vidl(ac)

—

0.44

Input AC differential cross point voltage3

Vix(ac)

Relative to Vref

-0.12

0.12

Over/undershoot peak

Vpeak

—

0.35

Over/undershoot area (above OVDD

or below OVSS)

Varea

400 MHz

—

0.3

V-ns

Single output slew rate, measured between

Vol(ac) and Voh(ac)

tsr

Ω to Vref.

5 pF load.

Drive impedance = 40

± 30%

1.5

3.5

V/ns

Ω to Vref.

5pF load.Drive

impedance = 60

Ω ±

30%

12.5

Skew between pad rise/fall asymmetry + skew

caused by SSN

tSKD

clk = 400 MHz

—

0.1

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