IMX6SDLCEC datasheet(82/169 Pages) NXP

82 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

Electrical Characteristics

4.11.5

Ethernet Controller (ENET) AC Electrical Specifications

The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive

at timing specs/constraints for the physical interface.

4.11.5.1

ENET MII Mode Timing

This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal

timings.

4.11.5.1.1

MII Receive Signal Timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER, and ENET_RX_CLK)

The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There

is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the

ENET_RX_CLK frequency.

Figure 43 shows MII receive signal timings. Table 55 describes the timing parameters (M1–M4) shown in

the figure.

Figure 43. MII Receive Signal Timing Diagram

1 ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.

Table 55. MII Receive Signal Timing

Characteristic1

Min

Max

Unit

ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to

ENET_RX_CLK setup

5—

ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER hold

5—

ENET_RX_CLK pulse width high

35%

65%

ENET_RX_CLK period

ENET_RX_CLK pulse width low

35%

65%

ENET_RX_CLK period

ENET_RX_CLK (input)

ENET_RX_DATA3,2,1,0

ENET_RX_ER

ENET_RX_EN

(inputs)

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