MIC33M350 datasheet(16/32 Pages) MICROCHIP

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MIC33M350

DS20006348B-page 16

 2020-2021 Microchip Technology Inc.

3.1

Power Ground Pin (PGND)

PGND is the ground path for the MIC33M350 buck

converter power stage. The PGND pin connects to the

sources of the low-side N-Channel MOSFETs, the

negative terminals of input capacitors and the negative

terminals of output capacitors. The loop for the Power

Ground should be as small as possible and separate

from the Analog Ground (AGND) loop.

3.2

Switch Node Pin (SW)

The SW pin connects directly to the switch node. The

Switching Node output pin is connected to the internal

MOSFETs and inductor. Due to the high-speed

switching on this pin, the SW pin should be routed

away from sensitive nodes. The SW pin also senses

the current by monitoring the voltage across the

low-side MOSFET during off-time.

3.3

Input Voltage Pin (PVIN)

This is an input supply to the source of the internal

high-side P-channel MOSFET. The PVIN operating

voltage range is from 2.4V to 5.5V. An input capacitor

between PVIN and the Power Ground (PGND) pin is

required and placed as close as possible to the IC.

3.4

Analog Voltage Input Pin (SVIN)

The power to the internal reference and control

sections of the MIC33M350. A 1.0 µF ceramic

capacitor from SVIN to ground must be used. Internally

connected to PVIN through a 10 resistor.

3.5

Output Voltage Selection Control

Pin 2 (VSEL2)

The Logic state of the VSEL1 and VSEL2 selects the

output voltage. This input has three Digital states: High,

Low and Floating. See Table 4-1.

3.6

Output Voltage Selection Control

Pin 1 (VSEL1)

The Logic state of the VSEL1 and VSEL2 selects the

output voltage. This input has three Digital states: High,

Low and Floating. See Table 4-1.

3.7

Enable Pin (EN)

Logic high enables operation of the regulator. Logic low

shuts down the device. In the OFF state, the supply

current to the device is greatly reduced (typically

1.5 µA). The EN pin should not be left open.

3.8

Power Good Pin (PG)

This is an open-drain output that indicates when the

output voltage is higher than the 91% limit. There is a

4% hysteresis, therefore, PG will return to low when the

falling output voltage falls below 87% of the target

regulation voltage.

3.9

Output Voltage Sense Pin (VOUT)

This pin is used to remotely sense the output voltage.

Connect it to VOUT as close to the output capacitor as

possible to sense output voltage. This pin also provides

the path to discharge the output through an internal

 resistor when it is disabled.

3.10

Analog Ground Pin (AGND)

This is an internal signal ground for all low-power

circuits. Connect it to ground plane. For the best load

regulation, the connection path from AGND to the output

capacitor ground terminal should be free from parasitic

voltage drops.

3.11

EP1_PGND, EP2_PGND

These pins electrically connected to the PGND pins.

They must be connected with thermal vias to the

ground plane to ensure adequate heat sinking.

3.12

EP_SW Exposed Pad (SW)

This pin is electrically connected to the SW node.

3.13

OUT Exposed Pad (OUT)

This pin is electrically connected to the OUT pins. It

must be externally connected to the output power

connection.

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