Data Sheet

ADP1974

Rev. 0 | Page 11 of 19

When operating with an input voltage above 50 V, additional

input filtering is recommended. Figure 21 shows the

recommended filter configuration.

VIN

SUPPLY > 50V

4.7µF

C

ADP1974

R

Figure 21. Recommended Filter Configuration for

Input Voltages Greater than 50 V

EN/SHUTDOWN

The EN input turns the ADP1974 on or off and can operate

from voltages up to 60 V. The EN pin is designed with precision

enable control. When the EN voltage is less than 1.22 V (typical),

the ADP1974 shuts down, VREG is disabled, and both DL and

DH are driven low. When the ADP1974 shuts down, the VIN

supply current is 15 μA (typical). When the EN voltage is greater

than 1.25 V (typical), the ADP1974 is enabled, and VREG ramps

to 5 V.

In addition to the EN pin, the device can be disabled via a fault

condition indicated by an internal TSD event, a UVLO condition

on VIN, or an external fault condition signaled via the FAULT pin.

It is necessary to disable the device to change the operating

mode from buck to boost.

UNDERVOLTAGE LOCKOUT (UVLO)

The UVLO function prevents the IC from turning on when the

input voltage is below the specified operating range to avoid an

undesired operating mode. When VIN rises, the UVLO does

not allow the ADP1974 to turn on unless VIN is greater than

5.71 V (typical). The UVLO disables the device when VIN

drops below 5.34 V (typical). The UVLO levels have ~370 mV

of hysteresis to prevent the system from turning on and off

repeatedly when there is a slow voltage ramp on the VIN pin.

SOFT START

The ADP1974 has a programmable soft start that prevents

output voltage overshoot during startup. When the ADP1974 is

enabled with the EN pin, the VREG voltage begins rising to 5 V.

When VREG reaches 90% of its 5 V (typical) value, the 5 μA

PWM duty cycle gradually increases, allowing the output

the internal VREG voltage (5 V typical). When the system duty

cycle set by COMP is less than the soft start duty cycle, the external

control loop takes control of the ADP1974. See Figure 22 for a

soft start diagram.

When the device shuts down or a fault is detected, an active

VREG

4.5V

VOUT

0.52V

0V

ENABLE

ADP1974

BEGIN

REGULATION

SYNCHRONOUS

OPERATION

Figure 22. Soft Start Diagram

The MODE pin controls the ADP1974 duty cycle generator and

affects the DL and DH signals during soft start. In buck mode,

a DH pulse initiates the on time (or Phase 1). In boost mode, a

DL pulse initiates the on time. For more information about

buck vs. boost operation, see the Operating Modes section.

During soft start, the ADP1974 operates in asynchronous mode,

and the synchronous FET is not driven. During the off cycle, the

diode in parallel to the low-side FET (buck mode) or the high-

side FET (boost mode) conducts the current until it reaches zero

or the next cycle begins. After the soft start period is completed

(SS > 4.5 V), the ADP1974 switches to full synchronous mode.

OPERATING MODES

The ADP1974 operates as a synchronous buck or boost controller.

When the MODE pin is driven high, above the 1.20 V (typical)

threshold, the ADP1974 operates in a buck configuration for

battery charging. If the MODE pin is driven low, below the

1.05 V (typical) threshold, the ADP1974 operates in a boost

configuration. A boost configuration is ideal for discharging

in battery formation applications. See Figure 23 and Figure 24

for the ADP1974 behavior in each mode. When the ADP1974

is enabled, the internal regulator connected to the VREG pin also

powers up. On the rising edge of VREG, the state of the MODE pin

is latched, preventing the mode of operation from being changed

while the device is enabled. To change between boost and buck

modes of operation, shut down or disable the ADP1974, adjust the

MODE pin to change the operating mode, and restart the system.

The operating mode can be changed when the EN pin is driven

low, the FAULT pin is driven low, or the ADP1974 is disabled

via a TSD event or UVLO condition. On the rising edge of the

FAULT control signal, the state of the MODE pin is latched,

preventing the mode of operation from being changed while

the device is enabled.