ADP1974ARUZ-R7 datasheet(14/19 Pages) AD

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ADP1974

Data Sheet

Rev. 0 | Page 14 of 19

APPLICATIONS INFORMATION

The ADP1974 has many programmable features that are

optimized and controlled for a given application. The ADP1974

provides pins for selecting the operating mode, controlling the

current limit, selecting an internal or external clock, setting the

operating frequency, phase shifting the operating frequency,

programming the dead time, programming the maximum duty

cycle, and adjusting the soft start.

BUCK OR BOOST SELECTION

To operate the ADP1974 in boost (recycle) mode, apply a

voltage less than 1.05 V (typical) to the MODE pin. To operate

the ADP1974 in buck (discharge) mode, drive the MODE pin

high, greater than 1.20 V (typical). The state of the MODE pin

can change only when the ADP1974 is shut down via the EN pin,

or is disabled via an external fault condition signaled on the

FAULT pin, there is a TSD event, or there is a UVLO condition.

SELECTING RS TO SET THE CURRENT LIMIT

See Figure 26 for the current-limit block diagram for peak current-

limit control. To set the current limit, use the following equation:

IPK (mA) = 100 mV/RS

(2)

where:

IPK is the desired peak current limit in mA.

RS is the sense resistor used to set the peak current limit in Ω.

When the ADP1974 is configured to operate in buck (charge)

mode, the internal current-limit threshold is set to 300 mV

(typical) and the negative valley current-limit threshold is set to

450 mV (typical). When the ADP1974 is configured to operate

in boost (recycle) mode, the internal current-limit threshold is

set to 500 mV (typical). The external resistor (RCL) offsets the

current properly to detect the peak in both buck and boost

operation. Set the RCL value to 20 kΩ. In operation, the

equations for setting the peak currents follow.

For buck (charge) mode, use the following:

VCL (BUCK) = (ICL) × (RCL) − (IPK) × (RS)

(3)

VNC (BUCK) = (ICL) × (RCL) + (IVL (NEG)) × (RS)

(4)

For boost (recycle) mode, use the following:

VCL (BOOST) = (ICL) × (RCL) + (IPK) × (RS)

(5)

where:

VCL (BUCK) = 300 mV typical.

ICL = 20 μA typical.

RCL = 20 kΩ.

IPK is the peak inductor current.

VNC (BUCK) = 450 mV typical.

IVL (NEG) is the valley inductor current.

VCL (BOOST) = 500 mV typical.

The ADP1974 is designed so that the peak current limit is the

same in both the buck mode and the boost mode of operation. A

1% or better tolerance for the RCL and RS resistors is recommended.

ADJUSTING THE OPERATING FREQUENCY

If the SCFG pin is tied to VREG, forcing VSCFG ≥ 4.53 V, or if

SCFG is left floating and internally tied to VREG, the ADP1974

operates at the frequency set by RFREQ, and the SYNC pin outputs

a clock at the programmed frequency. When VSCFG ≥ 4.53 V, the

output clock on the SYNC pin can be used as a master clock in

applications that require synchronization.

If VSCFG is ≤ 0.5 V, the SYNC pin is configured as an input, and

the ADP1974 operates as a slave device. As a slave device, the

ADP1974 synchronizes to the external clock applied to the SYNC

pin. If the voltage applied to the SCFG pin is 0.65 V < VSCFG <

4.25 V, and a resistor is connected between SCFG and ground,

the SYNC pin is configured as an input, and the ADP1974

synchronizes to a phase shifted version of the external clock

applied to the SYNC pin.

Whether operating the ADP1974 as a master or as a slave

device, carefully select RFREQ using the equations in the

following sections.

Selecting RFREQ for a Master Device

When VSCFG is ≥ 4.53 V, the ADP1974 operates as a master device.

When functioning as a master device, the ADP1974 operates at

the frequency set by the external RFREQ resistor connected

between FREQ and ground, and the ADP1974 outputs a clock

at the programmed frequency on the SYNC pin.

Figure 28 shows the relationship between the RFREQ (MASTER) value

and the programmed switching frequency.

210

110

130

150

170

190

100

150

200

250

300

fSET (kHz)

Figure 28. RFREQ (MASTER) vs. Switching Frequency (fSET)

To calculate the RFREQ (MASTER) value for a desired master clock

synchronization frequency, use the following equation:



(kHz)

kΩ

)

(

SET

MASTER

FREQ



(5)

where:

RFREQ (MASTER) is the resistor in kΩ to set the frequency for master

devices.

fSET is the switching frequency in kHz.

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