ADP1974ARUZ-R7 datasheet(18/19 Pages) AD

18 / 19 page

ADP1974

Data Sheet

Rev. 0 | Page 18 of 19

PCB LAYOUT GUIDELINES

For high efficiency, good regulation, and stability, a well designed

PCB layout is required.

Use the following guidelines when designing the PCB (see

Figure 20 for the block diagram and Figure 2 for the pin

configuration):



Keep the low effective series resistance (ESR) input supply

capacitor (CIN) for VIN as close as possible to the VIN and

GND pins to minimize noise injected into the device from

board parasitic inductance.



Keep the low ESR input supply capacitor (CVREG) for VREG as

close as possible to the VREG and GND pins to minimize the

noise injected into the device from board parasitic inductance.



Place the components for the SCFG, FREQ, DMAX, and SS

pins close to the corresponding pins. Tie these components

collectively to an analog ground plane that makes a Kelvin

connection to the GND pin.



Keep the trace from the COMP pin to the accompanying

device (for example, the AD8450) as short as possible. Avoid

routing this trace near switching signals, and shield the trace,

if possible.



Place any trace or components for the SYNC pin away from

sensitive analog nodes. When using an external pull-up

resistor, it is best to use a local 0.1 μF bypass capacitor from

the supply of the pull-up resistor to GND.



Keep the traces from the DH and DL pins to the external

components as short as possible to minimize parasitic

inductance and capacitance, which affect the control

signal. The DH and DL pins are switching nodes; do not

route them near any sensitive analog circuitry.



Keep high current traces as short and as wide as possible.



Connect the ground connection of the ADP1974 directly

to the ground connection of the current sense resistor (RS).



Connect CL through a 20 kΩ resistor directly to RS.



From the ground connection shown in Figure 32, connect

the following:



The GND pin to the ground point for RS



The system power ground bus to the ground point of RS



When building a system with a master and multiple slave

devices, minimize the capacitance of the trace attached to

the SYNC pin by considering the following items:



For small systems with only a few slave devices, a

resistor connected in series between the master SYNC

signal and the slave SYNC input pins limits the

capacitance of the trace and reduces the fast ground

currents that can inject noise into the master device.



For larger applications, the series resistance is not

enough to isolate the master SYNC clock. In larger

systems, use an external buffer to reduce the

capacitance of the trace. The external buffer has the

drive capability to support a large number of slave

devices.

GND

RCL

20kΩ

NMOS

POWER

FET

SOURCE

GROUND

BUS

Figure 32. Recommended RS Kelvin Ground Connection

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